公开(公告)号：US20110235412A1

公开(公告)日：2011-09-29

申请号：US13156763

申请日：2011-06-09

申请人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

发明人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/3427

摘要： A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

摘要翻译： 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

公开(公告)号：US07888218B2

公开(公告)日：2011-02-15

申请号：US11724775

申请日：2007-03-16

申请人： Zhizheng Liu ,  Shankar Sinha ,  Timothy Thurgate ,  Ming-Sang Kwan

发明人： Zhizheng Liu ,  Shankar Sinha ,  Timothy Thurgate ,  Ming-Sang Kwan

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： The present invention pertains to a system method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising forming adjacent first memory cell process assemblies; comprising a charge trapping dielectric, a first polysilicon layer and defining a first bitline opening there between, forming first polysilicon layer features over the charge trapping dielectric layer, depositing a layer of second spacer material over the charge trapping dielectric and the first polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the first polysilicon layer features to define a second bitline opening between the adjacent memory cells, performing a bitline implant, or pocket implants, or both into the bitline opening to establish buried bitlines within the substrate having respective bitline widths that are narrower than the respective widths of the first bitline openings, removing the sidewall spacers, and performing back end processing.

摘要翻译： 本发明涉及一种在半导体衬底上形成双位存储器芯阵列的至少一部分的系统方法，该方法包括形成相邻的第一存储单元处理组件; 包括电荷捕获电介质，第一多晶硅层并且在其间限定第一位线开口，在电荷俘获电介质层上形成第一多晶硅层特征，在电荷俘获电介质和第一多晶硅层特征之上沉积第二间隔物材料层， 形成与电荷俘获电介质相邻的侧壁间隔物，并且第一多晶硅层的特征在于限定相邻存储器单元之间的第二位线开口，执行位线注入或凹坑注入，或两者进入位线开口以在衬底内建立掩埋位线 具有比第一位线开口的相应宽度窄的各自的位线宽度，去除侧壁间隔件，以及执行后端处理。

公开(公告)号：US20100213535A1

公开(公告)日：2010-08-26

申请号：US12390550

申请日：2009-02-23

申请人： Gulzar A. Kathawala ,  Zhizheng Liu ,  Kuo Tung Chang ,  Lei Xue

发明人： Gulzar A. Kathawala ,  Zhizheng Liu ,  Kuo Tung Chang ,  Lei Xue

IPC分类号： H01L29/792 ,  H01L21/336 ,  H01L21/425

CPC分类号： H01L27/11568 ,  G11C16/10 ,  G11C16/3418 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11578

摘要： Semiconductor devices having reduced parasitic current and methods of malting the semiconductor devices are provided. Further provided are memory devices having reduced adjacent wordline disturb. The memory devices contain wordlines formed over a semiconductor substrate, wherein at least one wordline space is formed between the wordlines. Adjacent wordline disturb is reduced by implanting one or more of indium, boron, and a combination of boron and indium in the surface of the at least one wordline space.

摘要翻译： 提供具有降低的寄生电流的半导体器件和麦芽半导体器件的方法。 还提供了具有减少的相邻字线干扰的存储器件。 存储器件包含半导体衬底上形成的字线，其中在字线之间形成至少一个字线空间。 通过在至少一个字线空间的表面中注入铟，硼以及硼和铟的组合中的一种或多种来减少相邻的字线干扰。

公开(公告)号：US07750407B2

公开(公告)日：2010-07-06

申请号：US11612265

申请日：2006-12-18

申请人： Wei Zheng ,  Jean Yang ,  Mark Randolph ,  Ming Kwan ,  Yi He ,  Zhizheng Liu ,  Meng Ding

发明人： Wei Zheng ,  Jean Yang ,  Mark Randolph ,  Ming Kwan ,  Yi He ,  Zhizheng Liu ,  Meng Ding

IPC分类号： H01L29/76

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11531

摘要： A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.

摘要翻译： 半导体器件包括衬底和形成在衬底上的存储单元。 存储单元包括字线。 半导体器件还包括形成在衬底中的保护区域，被配置为将字线延伸到保护区域的导电结构以及被配置为使字线和保护区域短路的触点。

公开(公告)号：US07746705B2

公开(公告)日：2010-06-29

申请号：US11953689

申请日：2007-12-10

申请人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

发明人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

IPC分类号： G11C16/04

CPC分类号： G11C16/3418

摘要： A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.

摘要翻译： 提供了一种存储器件，其包括便于擦除基本上均匀的电磁场中的存储器单元的优化部件，以及便于在基本均匀的电磁场中擦除存储器单元的方法。 优化组件有助于同时选择要擦除的存储器单元的子集，使得存储器单元子集中的存储单元具有与存储单元相邻的两个相邻存储器单元，其位于存储器的子集中，或者相邻的一个相邻存储器单元 当存储器单元是端行存储单元时。 优化组件有助于执行Fowler-Nordheim信道擦除来擦除存储器单元的子集，并且与擦除命令相关联的预定电压电位被施加到存储器单元子集的每个单元，以便于减少与电磁场相关联的边缘效应 在擦除期间应用于细胞。

公开(公告)号：US20100103732A1

公开(公告)日：2010-04-29

申请号：US12650118

申请日：2009-12-30

申请人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

发明人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/3427

摘要： A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

摘要翻译： 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

公开(公告)号：US07671405B2

公开(公告)日：2010-03-02

申请号：US11646157

申请日：2006-12-26

申请人： Timothy Thurgate ,  Yi He ,  Ming-Sang Kwan ,  Zhizheng Liu ,  Xuguang Wang

发明人： Timothy Thurgate ,  Yi He ,  Ming-Sang Kwan ,  Zhizheng Liu ,  Xuguang Wang

IPC分类号： H01L27/112 ,  H01L21/336

CPC分类号： H01L27/11568 ,  G11C5/02 ,  G11C5/06 ,  H01L27/115

摘要： A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising performing front end processing, performing a first bitline implant, or pocket implants, or both into the first bitline spacings to establish buried first bitlines within the substrate, depositing a layer of the spacer material over the charge trapping dielectric and the polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the polysilicon layer features to define second bitline spacings between adjacent memory cells, performing a deep arsenic implant into the second bitline spacings to establish a second bitline within the structure that is deeper than the first bit line, removing the sidewall spacers and performing back end processing.

摘要翻译： 一种在半导体衬底上形成双位存储器核心阵列的至少一部分的方法，所述方法包括执行前端处理，执行第一位线注入或袋式注入或二者进入第一位线间隔以建立掩埋的第一位线 在衬底内，在电荷俘获电介质和多晶硅层特征之上沉积间隔物材料层，形成与电荷俘获电介质相邻的侧壁隔离层和多晶硅层特征以限定相邻存储器单元之间的第二位线间隔，执行深度 砷注入到第二位线间隔中，以在结构内建立比第一位线更深的第二位线，去除侧壁间隔件并执行后端处理。

公开(公告)号：US07626869B2

公开(公告)日：2009-12-01

申请号：US11745327

申请日：2007-05-07

申请人： Xuguang Wang ,  Yi He ,  Zhizheng Liu ,  Sung-Yong Chung ,  Darlene G. Hamilton ,  Ashot Melik-Martirosian ,  Gulzar Kathawala ,  Ming Sang Kwan ,  Mark Randolph ,  Timothy Thurgate

发明人： Xuguang Wang ,  Yi He ,  Zhizheng Liu ,  Sung-Yong Chung ,  Darlene G. Hamilton ,  Ashot Melik-Martirosian ,  Gulzar Kathawala ,  Ming Sang Kwan ,  Mark Randolph ,  Timothy Thurgate

IPC分类号： G11C11/34

CPC分类号： G11C16/16

摘要： Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.

摘要翻译： 同时删除字线可能会导致不良结果，因为某些字线受到其他字线的电磁波的影响。 然而，其他字线不受影响，因为它们在联系人旁边。 因此，删除允许擦除字线而不受其他字线影响的多相序列中的字线可能是有益的。

公开(公告)号：US07285827B1

公开(公告)日：2007-10-23

申请号：US11194449

申请日：2005-08-02

申请人： Yi He ,  Zhizheng Liu ,  Meng Ding ,  Wei Zheng

发明人： Yi He ,  Zhizheng Liu ,  Meng Ding ,  Wei Zheng

IPC分类号： H01L23/62

CPC分类号： H01L27/0266 ,  H01L27/0255

摘要： A device includes a memory device and an NPN or PNP diode coupled to a word-line of the memory device. The NPN or PNP diode reduces device damage and performance impairment that may result from device charging by drawing charges away from the memory device.

摘要翻译： 一种设备包括存储器件和耦合到存储器件的字线的NPN或PNP二极管。 NPN或PNP二极管通过从存储器件中抽取电荷来减少设备充电所造成的器件损坏和性能损害。

公开(公告)号：US07269067B2

公开(公告)日：2007-09-11

申请号：US11174560

申请日：2005-07-06

申请人： Shankar Sinha ,  Zhizheng Liu ,  Yi He

发明人： Shankar Sinha ,  Zhizheng Liu ,  Yi He

IPC分类号： G11C11/34

CPC分类号： H01L29/7923 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568

摘要： A method of programming a memory cell in a non-volatile memory device includes applying a first voltage to a control gate associated with the memory cell and applying a second voltage to a drain region associated with the memory cell. The method also includes applying a positive bias to a source region associated with the memory cell and/or applying a negative bias to a substrate region associated with the memory cell.

摘要翻译： 一种对非易失性存储器件中的存储器单元进行编程的方法包括：将第一电压施加到与存储器单元相关联的控制栅极，并将第二电压施加到与存储器单元相关联的漏极区域。 该方法还包括向与存储器单元相关联的源极区域施加正偏压和/或将负偏压施加到与存储器单元相关联的衬底区域。