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46 条记录 (耗时 0.028 秒)

    MRAM cells and circuit for programming the same
    26.
    发明授权
    MRAM cells and circuit for programming the same 有权
    MRAM单元和电路编程相同

    公开(公告)号：US08451655B2

    公开(公告)日：2013-05-28

    申请号：US13364955

    申请日：2012-02-02

    申请人： Shine Chung ,  Hung-Sen Wang ,  Tao-Wen Chung ,  Chun-Jung Lin ,  Yu-Jen Wang

    发明人： Shine Chung ,  Hung-Sen Wang ,  Tao-Wen Chung ,  Chun-Jung Lin ,  Yu-Jen Wang

    IPC分类号： G11C11/00

    CPC分类号： G11C11/1677 ,  G11C11/1675

    摘要： A circuit includes magneto-resistive random access memory (MRAM) cell and a control circuit. The control circuit is electrically coupled to the MRAM cell, and includes a current source configured to provide a first writing pulse to write a value into the MRAM cell, and a read circuit configured to measure a status of the MRAM cell. The control circuit is further configured to verify whether a successful writing is achieved through the first writing pulse.

    摘要翻译： 电路包括磁阻随机存取存储器（MRAM）单元和控制电路。 控制电路电耦合到MRAM单元，并且包括被配置为提供第一写入脉冲以将值写入MRAM单元的电流源和被配置为测量MRAM单元的状态的读取电路。 控制电路还被配置为验证通过第一写入脉冲是否实现了成功写入。

    Raising programming current of magnetic tunnel junctions by applying P-sub bias and adjusting threshold voltage
    27.
    发明授权
    Raising programming current of magnetic tunnel junctions by applying P-sub bias and adjusting threshold voltage 有权
    通过施加P-sub偏置和调整阈值电压来提高磁隧道结的编程电流

    公开(公告)号：US08270207B2

    公开(公告)日：2012-09-18

    申请号：US12687720

    申请日：2010-01-14

    申请人： Shine Chung ,  Tao-Wen Chung ,  Chun-Jung Lin ,  Yu-Jen Wang

    发明人： Shine Chung ,  Tao-Wen Chung ,  Chun-Jung Lin ,  Yu-Jen Wang

    IPC分类号： G11C11/00

    CPC分类号： G11C11/1675 ,  G11C11/1659 ,  G11C11/1673

    摘要： A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device and a word line selector having a source-drain path serially coupled to the MTJ device. A negative substrate bias voltage is connected to a body of the word line selector to increase the drive current of the word line selector. The threshold voltage of the word line selector is also reduced.

    摘要翻译： 操作磁阻随机存取存储器（MRAM）单元的方法包括提供包括磁隧道结（MTJ）器件的MRAM单元和具有串联耦合到MTJ器件的源极 - 漏极路径的字线选择器。 负极衬底偏置电压连接到字线选择器的主体以增加字线选择器的驱动电流。 字线选择器的阈值电压也减小。

    MRAM with current-based self-referenced read operations
    28.
    发明授权
    MRAM with current-based self-referenced read operations 有权
    MRAM具有基于当前的自引用读操作

    公开(公告)号：US08493776B1

    公开(公告)日：2013-07-23

    申请号：US13364756

    申请日：2012-02-02

    申请人： Hung-Chang Yu ,  Kai-Chun Lin ,  Yu-Der Chih ,  Chun-Jung Lin

    发明人： Hung-Chang Yu ,  Kai-Chun Lin ,  Yu-Der Chih ,  Chun-Jung Lin

    IPC分类号： G11C11/00

    CPC分类号： G11C11/1673 ,  G11C13/004 ,  G11C29/74

    摘要： A magnetoresistive memory stores logic values in high and low resistance states of magnetic tunnel junction elements. Instead of comparing the resistance of elements to a fixed threshold to discern a logic state, the resistances of elements are self-compared before and after imposing a low resistance state. A measure of the resistance of an element in its unknown resistance state is stored, for example by charging a capacitor to a voltage produced when read current bias is applied. Then the element is written into its low resistance state and read current bias is applied again to develop another voltage, representing the low resistance state. A comparison circuit using current summing and an offset providing a minimum difference tolerance determines whether the resistance of the element was changed or remained the same. This determines the logic state of the element.

    摘要翻译： 磁阻存储器将逻辑值存储在磁性隧道结元件的高电阻和低电阻状态中。 代替将元件的电阻与固定阈值进行比较以辨别逻辑状态，元件的电阻在施加低电阻状态之前和之后自我比较。 例如，通过将电容器充电到施加读取电流偏压时产生的电压来存储元件在其未知电阻状态下的电阻的量度。 然后将元件写入其低电阻状态，并再次施加读取电流偏压以产生表示低电阻状态的另一电压。 使用电流求和和提供最小差容差的偏移的比较电路确定元件的电阻是改变还是保持相同。 这决定了元素的逻辑状态。

    Piezoelectric buzzer
    29.
    发明申请
    Piezoelectric buzzer 失效
    压电式蜂鸣器

    公开(公告)号：US20090033473A1

    公开(公告)日：2009-02-05

    申请号：US11882413

    申请日：2007-08-01

    申请人： Cheng-Sheng Yu ,  Huey-Lin Hsieh ,  Tsai-Kun Huang ,  Jyh-Jang Wey ,  Wu-Song Chuang ,  Chun-Jung Lin

    发明人： Cheng-Sheng Yu ,  Huey-Lin Hsieh ,  Tsai-Kun Huang ,  Jyh-Jang Wey ,  Wu-Song Chuang ,  Chun-Jung Lin

    IPC分类号： G08B3/10

    CPC分类号： G10K9/122 ,  G10K9/22

    摘要： A piezoelectric buzzer includes a housing unit, a buzzer unit, and first and second terminals. The housing unit includes first and second housings coupled together. The second housing includes a base plate and a pair of spaced apart insert seats, each of which protrudes inwardly from the base plate toward the first housing and is formed with an insert hole. The buzzer unit is disposed in the resonant chamber and includes a vibrating plate and a piezoelectric plate attached to the vibrating plate. The first and second terminals are inserted respectively into the insert holes of the insert seats, and have a respective connection section extending outwardly of the housing unit, and a respective extending section abutting against a respective one of the vibrating plate and the piezoelectric plate.

    摘要翻译： 压电蜂鸣器包括壳体单元，蜂鸣器单元以及第一和第二端子。 壳体单元包括联接在一起的第一和第二壳体。 第二壳体包括基板和一对间隔开的插入座，每个插入座从基板朝向第一壳体向内突出并形成有插入孔。 蜂鸣器单元设置在谐振室中，并且包括振动板和附接到振动板的压电板。 第一和第二端子分别插入到插入座的插入孔中，并且具有从壳体单元向外延伸的相应的连接部分以及抵靠振动板和压电板中的相应一个的相应的延伸部分。

    Method for forming cells array of mask read only memory
    30.
    发明授权
    Method for forming cells array of mask read only memory 有权

    公开(公告)号：US06599680B2

    公开(公告)日：2003-07-29

    申请号：US09811392

    申请日：2001-03-20

    申请人： Chun-Jung Lin

    发明人： Chun-Jung Lin

    IPC分类号： G03F700

    CPC分类号： H01L27/11253 ,  H01L27/112

    摘要： A method for forming cells array of mask read only memory, at least includes: form numerous gate structures on substrate; form numerous doped regions in uncovered part of substrate; form first conductor layer on uncovered part of substrate with a thickness essentially equal to thickness of gate structures; form first dielectric layer on first conductor layer; form second conductor layer on both gate structures and first dielectric layer; perform a pattern transform process for transferring both second conductor layer and gate structures into conductor lines as word lines; form second dielectric layer on sidewalls of conductor lines to form spacer; form code photoresist on second conductor layer; and perform ions implantation process for implant numerous ions into partial substrate which is not covered by code photoresist.