公开(公告)号：US20070034517A1

公开(公告)日：2007-02-15

申请号：US11197009

申请日：2005-08-04

申请人： Jung-Chih Tsao ,  Kei-Wei Chen ,  Yu-Ku Lin ,  Chyi Chern

发明人： Jung-Chih Tsao ,  Kei-Wei Chen ,  Yu-Ku Lin ,  Chyi Chern

IPC分类号： B05D5/12 ,  C25D5/02

CPC分类号： C25D5/10 ,  C25D5/18 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76847 ,  H01L21/76877

摘要： An interconnect structure for a semiconductor device and its method of manufacture is described. The interconnect structure comprises a multi-layer structure having one or more stress-relief layers. In an embodiment, stress-relief layers are positioned between layers of electroplated copper or other conductive material. The stress-relief layer counteracts stress induced by the conductive material and helps prevent or reduce a pull-back void. For an interconnect structure using electroplated copper, the stress-relief layer may be formed by temporarily reducing the electroplating current, thereby causing a thin film of copper having a larger grain size to be formed between other layers of copper. The larger grain size typically exhibits more of a compressive stress than copper with a smaller grain size. The stress relief layer may also be formed of other materials, such as SIP-Cu, Ta, SiC, or the like.

摘要翻译： 描述了半导体器件的互连结构及其制造方法。 互连结构包括具有一个或多个应力消除层的多层结构。 在一个实施例中，应力消除层位于电镀铜或其它导电材料的层之间。 应力消除层抵消由导电材料引起的应力，并有助于防止或减少拉回空隙。 对于使用电镀铜的互连结构，可以通过暂时减少电镀电流来形成应力消除层，从而在其它铜层之间形成具有较大晶粒尺寸的铜的薄膜。 较大的晶粒尺寸通常表现出比具有较小晶粒尺寸的铜更多的压缩应力。 应力消除层也可以由其它材料形成，例如SIP-Cu，Ta，SiC等。

公开(公告)号：US07969708B2

公开(公告)日：2011-06-28

申请号：US11933919

申请日：2007-11-01

申请人： Jung-Chih Tsao ,  Miao-Cheng Liao ,  Phil Sun ,  Kei-Wei Chen

发明人： Jung-Chih Tsao ,  Miao-Cheng Liao ,  Phil Sun ,  Kei-Wei Chen

IPC分类号： H01G4/06

CPC分类号： H01G4/008 ,  H01G4/33 ,  H01L28/65

摘要： A method for forming an alpha-tantalum layer comprising disposing a nitrogen containing base layer on a semiconductor substrate, bombarding the nitrogen containing base layer with a bombarding element, thereby forming an alpha-tantalum seed layer, and sputtering a layer of tantalum on the alpha-tantalum seed layer, thereby forming a surface layer of substantially alpha-tantalum.

摘要翻译： 一种用于形成α-钽层的方法，包括在半导体衬底上设置含氮基底层，用轰击元件轰击含氮基底层，从而形成α-钽种子层，并且在该α层上溅射一层钽 钽籽晶层，从而形成基本上为α-钽的表面层。

公开(公告)号：US20090116169A1

公开(公告)日：2009-05-07

申请号：US11933919

申请日：2007-11-01

申请人： Jung-Chih Tsao ,  Miao-Cheng Liao ,  Phil Sun ,  Kei-Wei Chen

发明人： Jung-Chih Tsao ,  Miao-Cheng Liao ,  Phil Sun ,  Kei-Wei Chen

IPC分类号： H01G4/06 ,  C23C14/34

CPC分类号： H01G4/008 ,  H01G4/33 ,  H01L28/65

摘要： A method for forming an alpha-tantalum layer comprising disposing a nitrogen containing base layer on a semiconductor substrate, bombarding the nitrogen containing base layer with a bombarding element, thereby forming an alpha-tantalum seed layer, and sputtering a layer of tantalum on the alpha-tantalum seed layer, thereby forming a surface layer of substantially alpha-tantalum.

摘要翻译： 一种用于形成α-钽层的方法，包括在半导体衬底上设置含氮基底层，用轰击元件轰击含氮基底层，从而形成α-钽种子层，并且在该α层上溅射一层钽 钽籽晶层，从而形成基本上为α-钽的表面层。

公开(公告)号：US20050121329A1

公开(公告)日：2005-06-09

申请号：US10731331

申请日：2003-12-05

申请人： Jung-Chih Tsao ,  Kei-Wei Chen ,  Chi-Wen Liu ,  Shi-Chi Lin ,  Ray Chuang

发明人： Jung-Chih Tsao ,  Kei-Wei Chen ,  Chi-Wen Liu ,  Shi-Chi Lin ,  Ray Chuang

IPC分类号： C25D5/02 ,  C25D5/06 ,  C25D7/12 ,  C25D17/14 ,  H01L21/288

CPC分类号： H01L21/2885 ,  C25D5/06 ,  C25D17/001 ,  C25D17/14

摘要： A thrust pad assembly which is capable of reducing the quantity of metal electroplated onto the edge region of a substrate to eliminate or reduce the need for edge bevel cleaning or removal of excess metal from the substrate after the electroplating process. The thrust pad assembly includes an air platen through which air is applied at variable pressures to the central and edge regions, respectively, of a thrust pad. The thrust pad applies pressure to a contact ring connected to an electroplating voltage source. The contact ring applies relatively less pressure to the edge region than to the central region of the substrate, thereby reducing the ohmic contact.

摘要翻译： 一种止推垫组件，其能够减少电镀到基板的边缘区域上的金属的量，以消除或减少在电镀工艺之后边缘斜面清洁或从基板上去除多余的金属的需要。 推力垫组件包括空气压板，空气压板分别通过空气压板以可变的压力施加到推力垫的中心和边缘区域。 推力垫对连接到电镀电压源的接触环施加压力。 接触环对边缘区域的压力相对于衬底的中心区域施加相对较小的压力，由此减小欧姆接触。

公开(公告)号：US20100230815A1

公开(公告)日：2010-09-16

申请号：US12785618

申请日：2010-05-24

申请人： Jung-Chih Tsao ,  Kei-Wei Chen ,  Yu-Ku Lin

发明人： Jung-Chih Tsao ,  Kei-Wei Chen ,  Yu-Ku Lin

IPC分类号： H01L23/522 ,  H01L23/48

CPC分类号： H01L23/5226 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Semiconductor devices and methods for fabricating the same. An exemplary device includes a substrate, a dielectric layer, a protection layer, and a conformal barrier layer. The dielectric layer overlies the substrate and comprises an opening. The opening comprises a lower portion and a wider upper portion, exposing parts of the substrate. The bottoms of the upper portion act as shoulders of the opening. The protection layer overlies at least one shoulder of the opening. The conformal barrier layer is disposed in the opening and overlies the protection layer and the dielectric layer, wherein etching resistance of the protection layer against inert-gas plasma is higher than that of the barrier layer.

摘要翻译： 半导体器件及其制造方法。 示例性器件包括衬底，电介质层，保护层和共形阻挡层。 电介质层覆盖在衬底上并且包括开口。 开口包括下部和较宽的上部，暴露基底的部分。 上部的底部作为开口的肩部。 保护层覆盖开口的至少一个肩部。 共形阻挡层设置在开口中并覆盖保护层和电介质层，其中保护层对惰性气体等离子体的耐蚀性高于阻挡层的抗蚀性。

公开(公告)号：US07208404B2

公开(公告)日：2007-04-24

申请号：US10687183

申请日：2003-10-16

申请人： Jung-Chih Tsao ,  Chi-Wen Li ,  Kei-Wei Chen ,  Jye-Wei Hsu ,  Hsien-Pin Fong ,  Steven Lin ,  Ray Chuang

发明人： Jung-Chih Tsao ,  Chi-Wen Li ,  Kei-Wei Chen ,  Jye-Wei Hsu ,  Hsien-Pin Fong ,  Steven Lin ,  Ray Chuang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76877 ,  H01L21/288 ,  H01L21/7684

摘要： A method of forming a copper interconnect in an opening within a pattern is described. The copper interconnect has an Rs that is nearly independent of opening width and pattern density. A first copper layer having a concave upper surface and thickness t1 is formed in a via or trench in a dielectric layer by depositing copper and performing a first CMP step. A second copper layer with a thickness t2 where t2≦t1 and having a convex lower surface is deposited on the first copper layer by a selective electroplating method. The first and second copper layers are annealed and then a second CMP step planarizes the second copper layer to become coplanar with the dielectric layer. The invention is also a copper interconnect comprised of the aforementioned copper layers where the first copper layer has a grain density (GD1)≧GD2 for the second copper layer.

摘要翻译： 描述了在图案内的开口中形成铜互连的方法。 铜互连具有几乎独立于开口宽度和图案密度的Rs。 通过沉积铜并执行第一CMP步骤，在电介质层中的通孔或沟槽中形成具有凹上表面和厚度t 1的第一铜层。 具有厚度为2 的第二铜层，其中具有凸下表面的第二铜层沉积在第一铜层上 通过选择性电镀方法。 对第一和​​第二铜层进行退火，然后第二CMP步骤将第二铜层平坦化成与电介质层共面。 本发明也是由上述铜层构成的铜布线，其中第一铜层具有第二铜层的晶粒密度（G SUB D1）= G D2 D2。

公开(公告)号：US07122471B2

公开(公告)日：2006-10-17

申请号：US10835315

申请日：2004-04-28

申请人： Jung-Chih Tsao ,  Chi-Wen Liu ,  Si-Kua Cheng ,  Che-Tsao Wang ,  Steven Lin ,  Hsien-Ping Feng ,  Chen-Peng Fan

发明人： Jung-Chih Tsao ,  Chi-Wen Liu ,  Si-Kua Cheng ,  Che-Tsao Wang ,  Steven Lin ,  Hsien-Ping Feng ,  Chen-Peng Fan

IPC分类号： H01L21/44 ,  H01L21/42 ,  H01L21/268 ,  H01L21/428

CPC分类号： H01L21/68728 ,  H01L21/67109 ,  H01L21/68707 ,  H01L21/76877

摘要： A novel method for preventing the formation of voids in metal interconnects fabricated on a wafer, particularly during a thermal anneal process, is disclosed. The method includes fabricating metal interconnects between metal lines on a wafer. During a thermal anneal process carried out to reduce electrical resistance of the interconnects, the wafer is positioned in spaced-apart relationship to a wafer heater. This spacing configuration facilitates enhanced stabilility and uniformity in heating of the wafer by reducing the presence of particles on and providing a uniform flow of heated air or gas against and the wafer backside. This eliminates or at least substantially reduces the formation of voids in the interconnects during the anneal process.

摘要翻译： 公开了一种用于防止在晶片上制造的金属互连中空隙形成的新方法，特别是在热退火工艺期间。 该方法包括在晶片上的金属线之间制造金属互连。 在进行用于降低互连的电阻的热退火工艺期间，晶片以与晶片加热器隔开的关系定位。 这种间隔结构通过减少加热的空气或气体抵靠和晶片背面的颗粒的存在而提高晶片加热的稳定性和均匀性。 这在退火过程中消除或至少基本上减少了互连件中空隙的形成。

公开(公告)号：US20060000717A1

公开(公告)日：2006-01-05

申请号：US10880675

申请日：2004-06-30

申请人： Hsien-Ping Feng ,  Ming-Yuang Cheng ,  Si-Kwua Cheng ,  Steven Lin ,  Jung-Chih Tsao ,  Chen-Peng Fan ,  Chi-Wen Liu

发明人： Hsien-Ping Feng ,  Ming-Yuang Cheng ,  Si-Kwua Cheng ,  Steven Lin ,  Jung-Chih Tsao ,  Chen-Peng Fan ,  Chi-Wen Liu

IPC分类号： C25D21/06

CPC分类号： H01L21/2885 ,  C25D21/06 ,  C25D21/18

摘要： A method of stabilizing plating film impurities in an electrochemical plating bath solution is disclosed. The method includes providing an electrochemical plating machine in which an electrochemical plating process is carried out. A by-product bath solution is formed by continually removing a pre-filtered bath solution from the machine and removing an additive from the pre-filtered bath solution. A clean bath solution is formed by removing an additive by-product from the by-product bath solution. An additive bath solution is formed by adding a fresh additive to the clean bath solution. The additive bath solution is added to the electrochemical plating machine. An apparatus for stabilizing film impurities in an electrochemical plating bath solution is also disclosed.

公开(公告)号：US07667835B2

公开(公告)日：2010-02-23

申请号：US11510951

申请日：2006-08-28

申请人： Hsi-Kuei Cheng ,  Jung-Chih Tsao ,  Hsien-Ping Feng ,  Ming-Yuan Cheng ,  Steven Lin ,  Ray Chuang

发明人： Hsi-Kuei Cheng ,  Jung-Chih Tsao ,  Hsien-Ping Feng ,  Ming-Yuan Cheng ,  Steven Lin ,  Ray Chuang

IPC分类号： G01N21/00 ,  G01N21/55 ,  G01B11/28 ,  C25D21/12 ,  H01L21/00

CPC分类号： C25D17/00 ,  C25D7/123 ,  C25D17/001 ,  C25D21/12 ,  G01N21/55 ,  G01N2021/8411 ,  H01L21/67005 ,  H01L21/67253

摘要： An apparatus and method for preventing the peeling of electroplated metal from a wafer, is disclosed. The apparatus includes a seed layer detector system having a light source and a reflectivity detector. According to the method, the light source emits a beam of light onto a wafer and the reflectivity detector receives the light reflected from the wafer. The reflectivity of the wafer surface is measured to determine the presence or absence of a seed layer on the wafer, as well as whether the seed layer has a minimum thickness for optimum electroplating of a metal onto the seed layer.

摘要翻译： 公开了一种用于防止电镀金属从晶片剥离的装置和方法。 该装置包括具有光源和反射率检测器的种子层检测器系统。 根据该方法，光源将光束发射到晶片上，反射率检测器接收从晶片反射的光。 测量晶片表面的反射率以确定晶片上晶种层的存在或不存在，以及种子层是否具有用于最佳电镀金属到籽晶层上的最小厚度。

公开(公告)号：US07432192B2

公开(公告)日：2008-10-07

申请号：US11347946

申请日：2006-02-06

申请人： Hsien-Ping Feng ,  Jung-Chih Tsao ,  Hsi-Kuei Cheng ,  Chih-Tsung Lee ,  Ming-Yuan Cheng ,  Steven Lin ,  Ray Chuang ,  Chi-Wen Liu

发明人： Hsien-Ping Feng ,  Jung-Chih Tsao ,  Hsi-Kuei Cheng ,  Chih-Tsung Lee ,  Ming-Yuan Cheng ,  Steven Lin ,  Ray Chuang ,  Chi-Wen Liu

IPC分类号： H01L21/4763

CPC分类号： H01L21/76877 ,  H01L21/2885

摘要： A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cm2 current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a H2 plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm2 current density and second deposition step at a 60 mA/cm2 current density is used to deposit a second copper layer that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.

摘要翻译： 描述了在双镶嵌方案中形成铜互连的方法。 在扩散阻挡层和种子层依次形成在电介质层中的沟槽和通孔的侧壁和底部上之后，通过第一ECP工艺以10mA / cm 2 / >电流密度以填充通孔和部分沟槽。 进行第一退火步骤以除去碳杂质，并且任选地包括H 2 O 3等离子体处理。 使用在40mA / cm 2电流密度下的第一沉积步骤和以60mA / cm 2电流密度进行第二沉积步骤的第二个ECP工艺来沉积 第二铜层超过沟槽。 在第二退火步骤之后，CMP工艺使铜层平坦化。 通过该方法可以实现更少的铜缺陷，降低的S，Cl和C杂质，以及Rc性能的提高。