公开(公告)号：US06811410B2

公开(公告)日：2004-11-02

申请号：US10156909

申请日：2002-05-28

申请人： David G. Figueroa ,  Yuan-Liang Li

发明人： David G. Figueroa ,  Yuan-Liang Li

IPC分类号： H01R1200

CPC分类号： H05K1/0231 ,  H01R12/7088 ,  H01R13/6625 ,  H01R31/08 ,  H01R33/765 ,  H05K2201/10325 ,  H05K2201/10689

摘要： An integrated circuit socket with capacitors and shunts is disclosed. According to one embodiment of the invention, a socket is divided into a shunt area, a socket pin area, and a land side capacitor area. The shunt area may contain a variable number of power shunts, ground shunts, and capacitors. The capacitors are connected across, and serve to decouple, power shunts and ground shunts. The shunts are to supply an electrical current from the capacitors to an integrated circuit device. The socket pin area may be surrounded by a metal fence serving as to lessen electromagnetic interference and as a ground and/or signal reference. The fence may be divided into sub-areas each comprising a coaxial differential signal pin opening pair. In alternate designs, an elongated power bar may serve as a power or ground shunt and may be used with several capacitors.

摘要翻译： 公开了一种具有电容器和分流器的集成电路插座。 根据本发明的一个实施例，插座被分成分流区域，插座引脚区域和陆侧电容器区域。 分流区域可能包含可变数量的功率分流器，接地分流器和电容器。 电容器连接在一起，并用于去耦电源分流器和接地分流器。 分流器将从电容器向集成电路器件提供电流。 插座针脚区域可以被金属围栏包围，以减少电磁干扰，并且作为接地和/或信号参考。 栅栏可以被划分成各自包括同轴差分信号针开口对的子区域。 在替代设计中，细长的电源杆可以用作电源或接地分流器，并且可以与多个电容器一起使用。

公开(公告)号：US06388207B1

公开(公告)日：2002-05-14

申请号：US09751356

申请日：2000-12-29

申请人： David G. Figueroa ,  Michael Walk ,  Yuan-Liang Li ,  Robert L. Sankman

发明人： David G. Figueroa ,  Michael Walk ,  Yuan-Liang Li ,  Robert L. Sankman

IPC分类号： H01R2368

CPC分类号： H05K1/115 ,  H01L23/49805 ,  H01L23/50 ,  H01L23/5383 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K1/0263 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/09854 ,  H01L2224/05599

摘要： To accommodate the operational and structural requirements of high performance integrated circuits, an integrated circuit package includes conductive trenches that are formed within a substrate. The trenches provide increased current carrying capacity, lower inductance, higher capacitance, and single and/or dual reference planes for signal conductors. Trench structures can be provided at various locations within the substrate, such as adjacent to signal conductors and embedded capacitors, as well as on the substrate periphery to couple the package to a socket. Trenches can be formed by routing, drilling, imprinting, and/or microperforation. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

摘要翻译： 为了适应高性能集成电路的操作和结构要求，集成电路封装包括形成在衬底内的导电沟槽。 沟槽提供增加的载流能力，较低的电感，更高的电容，以及用于信号导体的单和/或双参考平面。 沟槽结构可以设置在衬底内的各个位置，例如与信号导体和嵌入式电容器相邻，以及在衬底周边上以将封装耦合到插座。 可以通过布线，钻孔，压印和/或微穿孔形成沟槽。 还描述了制造方法以及将包装应用于电子组件和电子系统。

公开(公告)号：US07417872B2

公开(公告)日：2008-08-26

申请号：US11459951

申请日：2006-07-26

申请人： Yuan-Liang Li ,  Jiangqi He ,  Dong Zhong ,  David G. Figueroa

发明人： Yuan-Liang Li ,  Jiangqi He ,  Dong Zhong ,  David G. Figueroa

IPC分类号： H05H1/11

CPC分类号： H01P3/081 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H05K1/0242 ,  H05K1/0245 ,  H05K1/0265 ,  H05K3/4644 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/0979 ,  H05K2201/098 ,  H05K2203/0733 ,  H01L2924/00

摘要： Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.

摘要翻译： 用于承载高速数字差分信号的跟踪配置提供了降低的传导损耗和改善的信号完整性。 在一个实施例中，电路板具有布置在非导电材料上的第一组导电迹线和平行于第一组并设置在导电材料内的第二组导电迹线。 第二组与非导电材料与第一组分离。 第一组和第二组的相应迹线可以是堆叠配置。 在其他实施例中，导电材料可以设置在第一组和第二组的相应迹线之间，导致“I形”或“U形”横截面。 在其它实施例中，迹线构造具有“T形”和“L形”横截面。

公开(公告)号：US07286368B2

公开(公告)日：2007-10-23

申请号：US10976716

申请日：2004-10-29

申请人： Dong Zhong ,  David G. Figueroa ,  Yuan-Liang Li ,  Michael M. Desmith

发明人： Dong Zhong ,  David G. Figueroa ,  Yuan-Liang Li ,  Michael M. Desmith

IPC分类号： H05K7/00

CPC分类号： H01L23/50 ,  H01L2224/16225 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19106

摘要： According to some embodiments, a system includes an integrated circuit package to support an integrated circuit die. The integrated circuit package may include a plurality of conductive contacts and a decoupling capacitor. The decoupling capacitor may include a positive terminal contact pad coupled to a first one of the plurality of conductive contacts, the positive terminal contact pad comprising a first substantially non-conductive area, and a negative terminal contact pad coupled to a second one of the plurality of conductive contacts, the negative terminal contact pad comprising a second substantially non-conductive area.

摘要翻译： 根据一些实施例，系统包括用于支撑集成电路管芯的集成电路封装。 集成电路封装可以包括多个导电触点和去耦电容器。 去耦电容器可以包括耦合到多个导电触点中的第一个的正极端子接触焊盘，正极端子接触焊盘包括第一基本上不导电的区域，以及耦合到多个导电触点中的第二个的负极端子接触焊盘 的导电触点，负极接触焊盘包括第二基本上不导电的区域。

公开(公告)号：US07221046B2

公开(公告)日：2007-05-22

申请号：US10970237

申请日：2004-10-21

申请人： Dong Zhong ,  David G. Figueroa ,  Yuan-Liang Li

发明人： Dong Zhong ,  David G. Figueroa ,  Yuan-Liang Li

IPC分类号： H01L23/02

CPC分类号： H01L23/50 ,  H01L23/5386 ,  H01L24/17 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/19106 ,  H05K1/0231 ,  H05K1/167 ,  H01L2924/00 ,  H01L2224/0401

摘要： According to some embodiments, a system includes an integrated circuit package to support an integrated circuit die. The integrated circuit package may include a plurality of conductive contacts, and an element having a plurality of resistive portions, each of the plurality of resistive portions being coupled to a respective one of the plurality of conductive contacts. The integrated circuit package may further include a decoupling capacitor having a plurality of capacitor pads, each of the plurality of capacitor pads being coupled to a respective one of the plurality of resistive portions.

摘要翻译： 根据一些实施例，系统包括用于支撑集成电路管芯的集成电路封装。 集成电路封装可以包括多个导电触点，以及具有多个电阻部分的元件，多个电阻部分中的每一个耦合到多个导电触点中的相应一个。 集成电路封装还可以包括具有多个电容器焊盘的去耦电容器，所述多个电容器焊盘中的每一个耦合到所述多个电阻部分中的相应一个。

公开(公告)号：US06495770B2

公开(公告)日：2002-12-17

申请号：US09730210

申请日：2000-12-04

申请人： Yuan-Liang Li ,  David G. Figueroa ,  Priyavadan R. Patel

发明人： Yuan-Liang Li ,  David G. Figueroa ,  Priyavadan R. Patel

IPC分类号： H05K111

CPC分类号： H01L23/49822 ,  H01L23/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/15312 ,  H01L2224/05599

摘要： The invention provides an electronic assembly including a semiconductor chip and a semiconductor package substrate having power and ground shunts. The power and ground shunts of the semiconductor chip include contact pads on a surface thereof that are electrically connected to one another to protect electrical signal contacts on the contact pads from high, low-frequency current. The power shunt in the semiconductor package substrate connects one power plane to another and the ground shunts in the semiconductor package substrate connects one ground plane to another. The power and ground shunts in the semiconductor package substrate dictate terminal pins thereon from high, low-frequency current.

公开(公告)号：US20070295818A1

公开(公告)日：2007-12-27

申请号：US11473359

申请日：2006-06-22

申请人： Yuan-Liang Li ,  Jayashree Kar ,  David G. Figueroa ,  Dong Zhong

发明人： Yuan-Liang Li ,  Jayashree Kar ,  David G. Figueroa ,  Dong Zhong

IPC分类号： G06K7/10

CPC分类号： H05K1/0265 ,  H05K1/0254 ,  H05K2201/044 ,  H05K2201/0784 ,  H05K2201/093 ,  H05K2201/0969

摘要： A power plane including a supply power pin receptacle, a first connector power pin receptacle, and a second power pin receptacle, where a first electrical resistance between the supply power pin receptacle and the first connector power pin receptacle is substantially equal to a second electrical resistance between the supply power pin receptacle and the second connector power pin receptacle.

摘要翻译： 包括供电电源插座，第一连接器电源插座和第二电源插座的电力平面，其中电源电极插座和第一连接器电源插座之间的第一电阻基本上等于第二电阻 在电源插座和第二连接器电源插座之间。

公开(公告)号：US07212395B2

公开(公告)日：2007-05-01

申请号：US11024060

申请日：2004-12-28

申请人： Yuan-Liang Li ,  David G. Figueroa ,  Farzaneh Yahyaei-moayyed ,  Dong Zhong

发明人： Yuan-Liang Li ,  David G. Figueroa ,  Farzaneh Yahyaei-moayyed ,  Dong Zhong

IPC分类号： H01G4/228

CPC分类号： H01G4/012 ,  H01G4/232 ,  H01G4/30 ,  H01L2224/16 ,  H01L2924/15312 ,  H01L2924/19103 ,  H01L2924/19106 ,  H05K1/0231

摘要： According to some embodiments, a capacitor includes a first external capacitor plane including a first at least one terminal of a first polarity, and a first internal capacitor plane including a second at least one terminal of the first polarity. The second at least one terminal of the first polarity may be electrically coupled to the first at least one terminal of the first polarity, and a total area of the second at least one terminal of the first polarity may be less than a total area of the first at least one terminal of the first polarity.

摘要翻译： 根据一些实施例，电容器包括包括第一极性的第一至少一个端子的第一外部电容器平面和包括第一极性的第二至少一个端子的第一内部电容器平面。 第一极性的第二至少一个端子可以电耦合到第一极性的第一至少一个端子，并且第一极性的第二至少一个端子的总面积可以小于第一极性的总面积 第一极性的至少一个端子。

公开(公告)号：US06780057B2

公开(公告)日：2004-08-24

申请号：US10023834

申请日：2001-12-21

申请人： David G. Figueroa ,  Yuan-Liang Li

发明人： David G. Figueroa ,  Yuan-Liang Li

IPC分类号： H01R13648

CPC分类号： H05K7/1061 ,  H01L2224/16225 ,  H05K1/0219

摘要： A socket and fabrication method provide enhanced performance. The socket includes a base, and a plurality of signal contacts disposed within the base. A grounding fence is also disposed within the base such that the grounding fence laterally isolates the signal contacts from one another. The use of a grounding fence therefore enables elimination or significant reduction of ground contacts and therefore provides more signaling opportunities for a given amount of real estate.

公开(公告)号：US06519134B1

公开(公告)日：2003-02-11

申请号：US09619088

申请日：2000-07-19

申请人： Yuan-Liang Li ,  David G. Figueroa

发明人： Yuan-Liang Li ,  David G. Figueroa

IPC分类号： H01G4228

CPC分类号： H01G4/232

摘要： A design for capacitor terminals that includes connections to lowermost power and ground plates located within the bottom perimeter of the capacitor itself, for reducing loop inductance. The capacitor is particularly useful in combination with a circuit board, and especially in the power delivery system for a microprocessor.

摘要翻译： 电容器端子的设计，包括连接到位于电容器本身的底部周边内的最低功率和接地板，以减少环路电感。 电容器特别适用于电路板，特别是在用于微处理器的电力输送系统中。