公开(公告)号：US20250041721A1

公开(公告)日：2025-02-06

申请号：US18529441

申请日：2023-12-05

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Aaron Michael Knoll ,  Binh Huy Le ,  Madhusudhanan Srinivasan ,  Mark Richard Nutter

IPC: A63F13/52 ,  A63F13/355

Abstract: A server employs a shared raytracing context to generate video streams for multiple client devices. The server uses the shared raytracing context to perform raytracing operations for each of the client devices, and based on the raytracing operations generates different sets of image frames. The server then streams each set of image frames to a corresponding client device over a network.

公开(公告)号：US12216539B2

公开(公告)日：2025-02-04

申请号：US17977001

申请日：2022-10-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sudhanva Gurumurthi ,  Vilas Sridharan ,  Majed Valad Beigi

IPC: G06F11/30 ,  G06F11/07 ,  G06F11/10 ,  G06F12/1027

Abstract: A processing system employs techniques for enhancing dynamic random access memory (DRAM) page retirement to facilitate identification and retirement of pages affected by multi-page DRAM faults. In response to detecting an uncorrectable error at a first page of DRAM, the processing system identifies a second page of the DRAM for potential retirement based on one or more of physical proximity to the first page, inclusion in a range of addresses stored at a fault map that tracks addresses of DRAM pages having detected faults, and predicting a set of pages to check for faults based on misses at a translation lookaside buffer (TLB).

公开(公告)号：US20250039045A1

公开(公告)日：2025-01-30

申请号：US18915524

申请日：2024-10-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Jesse Barnes ,  Max Alt

IPC: H04L41/0823 ,  G06F9/48 ,  G06F9/50 ,  H04L12/46 ,  H04L47/70

Abstract: Systems, methods, and apparatuses are disclosed for implementation and management of a network of computing clusters and interfaces. In various examples, a dynamic supercomputing resource marketplace system includes a cluster network having one or more interconnected computing clusters. The dynamic supercomputing resource marketplace system includes a user interface system and/or an application program interface system for enabling a user to access the computing clusters. Advantageously, the dynamic supercomputing resource marketplace system facilitates increased utilization of computing clusters.

公开(公告)号：US20250036467A1

公开(公告)日：2025-01-30

申请号：US18745744

申请日：2024-06-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Sonu Arora ,  Daniel L. Bouvier

IPC: G06F9/50 ,  G06F1/3234 ,  G06F9/4401 ,  G06F12/02 ,  G06F12/1009 ,  G11C11/406 ,  G11C11/4074

Abstract: A method of operating a computing system includes storing a memory map identifying a first physical memory address as associated with a high performance memory and identifying a second physical memory address as associated with a low power consumption memory, servicing a first memory access request received from an application by accessing application data at the first physical memory address, in response to a change in one or more operating conditions of the computing system, moving the application data between the first physical memory address and the second physical memory address based on the memory map, and servicing a second memory access request received from the application by accessing the application data at the second physical memory address.

公开(公告)号：US12212337B2

公开(公告)日：2025-01-28

申请号：US18128943

申请日：2023-03-30

Applicant: XILINX, INC. ,  Advanced Micro Devices, Inc.

Inventor： Kumar Rahul ,  John J. Wuu ,  Santosh Yachareni

IPC: H03M13/11 ,  H03M13/00

Abstract: An integrated circuit (IC) device includes an error correction code (ECC) encoder circuitry configured to receive input data, determine min-terms in a Hamming matrix (H-Matrix) corresponding to the input data, and generate ECC data based on the min-terms and an output codeword based on the ECC data, and an error correction circuitry configured to generate a corrected output codeword based on the output codeword.

公开(公告)号：US20250029900A1

公开(公告)日：2025-01-23

申请号：US18784143

申请日：2024-07-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Deepak Vasant Kulkarni ,  Rahul Agarwal ,  Rajasekaran Swaminathan ,  Chintan Buch

IPC: H01L23/495 ,  H01L23/14 ,  H10B12/00

Abstract: Apparatuses, systems and methods for efficiently generating a package substrate. A semiconductor fabrication process (or process) fabricates each of a first glass package substrate and a second glass package substrate with a redistribution layer on a single side of a respective glass wafer. The process flips the second glass package substrate upside down and connects the glass wafers of the first and second glass package substrates together using a wafer bonding technique. In some implementations, the process uses copper-based wafer bonding. The resulting bonding between the two glass wafers contains no air gap, no underfill, and no solder bumps. Afterward, the side of the first glass package substrate opposite the glass wafer is connected to at least one integrated circuit. Additionally, the side of the second glass package substrate opposite the glass wafer is connected to a component on the motherboard through pads on the motherboard.

公开(公告)号：US12205897B2

公开(公告)日：2025-01-21

申请号：US17483672

申请日：2021-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L27/02

Abstract: A system and method for creating chip layout are described. In various implementations, a standard cell uses unidirectional tracks for power connections and signal routing. A single track of the metal one layer that uses a minimum width of the metal one layer is placed within a pitch of a single metal gate. The single track of the metal one layer provides a power supply reference voltage level or ground reference voltage level. This placement of the single track provides a metal one power post contacted gate pitch (CPP) of 1 CPP. To further reduce voltage droop, a standard cell uses dual height and half the width of a single height cell along with placing power posts with 1 CPP. The placement of the multiple power rails of the dual height cell allows alignment of the power rails with power rails of other standard cells.

公开(公告)号：US12204911B2

公开(公告)日：2025-01-21

申请号：US17497572

申请日：2021-10-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Matthew T. Sobel ,  Joshua James Lindner ,  Neil N. Marketkar ,  Kai Troester ,  Emil Talpes ,  Ashok Tirupathy Venkatachar

IPC: G06F9/38

Abstract: Systems, apparatuses, and methods for compressing multiple instruction operations together into a single retire queue entry are disclosed. A processor includes at least a scheduler, a retire queue, one or more execution units, and control logic. When the control logic detects a given instruction operation being dispatched by the scheduler to an execution unit, the control logic determines if the given instruction operation meets one or more conditions for being compressed with one or more other instruction operations into a single retire queue entry. If the one or more conditions are met, two or more instruction operations are stored together in a single retire queue entry. By compressing multiple instruction operations together into an individual retire queue entry, the retire queue is able to be used more efficiently, and the processor can speculatively execute more instructions without the retire queue exhausting its supply of available entries.

公开(公告)号：US12204900B2

公开(公告)日：2025-01-21

申请号：US17953142

申请日：2022-09-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S Jayasena

IPC: G06F9/30 ,  G06F15/78

Abstract: Predicates for processing in memory is described. In accordance with the described techniques, a predicate instruction to compute a conditional value based on data stored in a memory is provided to a processing-in-memory component. A response that includes the conditional value computed by the processing-in-memory component is received, and the conditional value is stored in a predicate register. One or more conditional instructions are provided to the processing-in-memory component based on the conditional value stored in the predicate register.

公开(公告)号：US12204459B2

公开(公告)日：2025-01-21

申请号：US17752244

申请日：2022-05-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Donald W. McCauley ,  William E. Jones

IPC: G06F12/08 ,  G06F12/0862 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/0846 ,  G06F12/0886

Abstract: A method, system, and processing system for pre-fetching data is disclosed. The method, system, and processing system includes data cache region prefetch circuitry for detecting a first access by a first instruction at a first instruction address to a first memory portion, detecting a first non-sequential access pattern to a set of addresses in the first memory portion, and in response to a miss by a second instruction at the first instruction address, and in response to the non-sequential access pattern occurring, pre-fetching data according to the first non-sequential access pattern.