公开(公告)号：US08918791B1

公开(公告)日：2014-12-23

申请号：US13045453

申请日：2011-03-10

Applicant: Keyur Chudgar ,  Vinay Ravuri ,  Kumar Sankaran

Inventor： Keyur Chudgar ,  Vinay Ravuri ,  Kumar Sankaran

IPC: G06F9/455 ,  G06F9/46

CPC classification number: G06F9/526

Abstract: A hardware-based method is provided for allocating shared resources in a system-on-chip (SoC). The SoC includes a plurality of processors and at least one shared resource, such as an input/output (IO) port or a memory. A queue manager (QM) includes a plurality of input first-in first-out memories (FIFOs) and a plurality of output FIFOs. A first application writes a first request to access the shared resource. A first application programming interface (API) loads the first request at a write pointer of a first input FIFO associated with the first processor. A resource allocator reads the first request from a read pointer of the first input FIFO, generates a first reply, and loads the first reply at a write pointer of a first output FIFO associated with the first processor. The first API supplies the first reply, from a read pointer of the first output FIFO, to the first application.

Abstract translation: 提供了一种基于硬件的方法来分配片上系统（SoC）中的共享资源。 SoC包括多个处理器和至少一个共享资源，诸如输入/输出（IO）端口或存储器。 队列管理器（QM）包括多个输入的先进先出存储器（FIFO）和多个输出FIFO。 第一个应用程序写入访问共享资源的第一个请求。 第一应用编程接口（API）在与第一处理器相关联的第一输入FIFO的写指针处加载第一请求。 资源分配器从第一输入FIFO的读指针读取第一请求，产生第一应答，并且在与第一处理器相关联的第一输出FIFO的写指针处加载第一应答。 第一个API从第一个输出FIFO的读指针向第一个应用提供第一个应答。

公开(公告)号：US08909061B1

公开(公告)日：2014-12-09

申请号：US13461847

申请日：2012-05-02

Applicant: Badri Varadarajan

Inventor： Badri Varadarajan

IPC: H04B10/00 ,  H04B10/04 ,  H04B10/12 ,  H04B10/06

CPC classification number: H04B10/6161 ,  H04B10/0775 ,  H04B10/25137

Abstract: A method is provided for performing chromatic dispersion (CD) pre-compensation. The method generates an electronic signal at a transmitter, and uses a transmit CD compensation estimate to compute a CD pre-compensation filter. The transmit CD pre-compensation filter is used to process the electronic signal, generating a pre-compensated electronic signal. The pre-compensated electronic signal is converted into an optical signal and transmitted to an optical receiver via an optical channel. In one aspect, the transmitter generates a test electronic signal and the CD compensation estimate uses a first dispersion value to compute a first CD compensation filter. The transmitter accepts a residual dispersion estimate of the test optical signal from the first optical receiver CD compensation filter, generated from a (receiver-side) CD estimate, and then the transmit CD estimate can be modified in response to the combination of the first dispersion value and residual dispersion estimate.

Abstract translation: 提供了一种用于执行色散（CD）预补偿的方法。 该方法在发射机处产生电子信号，并使用发射CD补偿估计来计算CD预补偿滤波器。 发射CD预补偿滤波器用于处理电子信号，产生预补偿的电子信号。 预补偿电子信号被转换成光信号，并通过光信道传输到光接收机。 在一个方面，发射机产生测试电子信号，并且CD补偿估计使用第一色散值来计算第一CD补偿滤波器。 发射机接收来自（接收机侧）CD估计产生的来自第一光接收机CD补偿滤波器的测试光信号的残余色散估计，然后响应于第一色散的组合来修改发送CD估计 值和残差分布估计。

公开(公告)号：US08907691B2

公开(公告)日：2014-12-09

申请号：US12490729

申请日：2009-06-24

Applicant: Joseph Martin Patterson

Inventor： Joseph Martin Patterson

IPC: G01R31/303 ,  G01R31/28

CPC classification number: G01R31/2875 ,  G01R31/303

Abstract: A system and method are provided for testing an integrated circuit (IC) using thermally induced noise analysis. The method provides an IC die and supplies electrical power to the IC die. The IC die surface is scanned with a laser, and the laser beam irradiated locations on the IC die surface are tracked. The laser scanning heats active electrical elements underlying the scanned IC die surface. A frequency response of an IC die electrical interface is measured and correlated to irradiated locations. IC die defect regions are determined in response to identifying location-correlated frequency measurements exceeding a noise threshold. For example, a frequency measurement may be correlated to a die surface location, and if frequency measurement exceeds the noise threshold, then circuitry underlying that surface area may be identified as defective. Typically, die defect regions are associated with measurements in the frequency range between about 1 Hertz and 10 kilohertz.

Abstract translation: 提供了一种使用热感应噪声分析测试集成电路（IC）的系统和方法。 该方法提供IC芯片并且为IC芯片提供电力。 利用激光扫描IC芯片表面，并跟踪IC芯片表面上的激光束照射位置。 激光扫描加热扫描IC芯片表面下方的有源电气元件。 测量IC芯片电接口的频率响应并将其与辐射位置相关联。 响应于识别超过噪声阈值的位置相关频率测量来确定IC芯片缺陷区域。 例如，频率测量可以与模具表面位置相关联，并且如果频率测量超过噪声阈值，则该表面积下面的电路可能被识别为有缺陷的。 通常，管芯缺陷区域在约1赫兹和10千赫兹之间的频率范围内的测量值相关联。

公开(公告)号：US08855258B1

公开(公告)日：2014-10-07

申请号：US13250794

申请日：2011-09-30

Applicant: Viet Do ,  Simon Pang

Inventor： Viet Do ,  Simon Pang

IPC: H04L7/00

CPC classification number: H04L7/033 ,  H04J3/076

Abstract: A system and method are provided for resynchronizing a transmission signal using a jitter-attenuated clock derived from an asynchronous gapped clock. A first-in first-out (FIFO) memory accepts an asynchronous gapped clock derived from a first clock having a first frequency. The gapped clock has an average second frequency less than the first frequency. The input serial stream of data is loaded at a rate responsive to the gapped clock. A dynamic numerator (DN) and dynamic denominator (DD) are iteratively calculated for the gapped clock, averaged, and an averaged numerator (A and an averaged denominator (AD) are generated. The first frequency is multiplied by the ratio of AN/AD to create a jitter-attenuated second clock having the second frequency. The FIFO memory accepts the jitter-attenuated second clock and supplies data from memory at the second frequency. A framer accepts the data from the FIFO memory and the jitter-attenuated second clock.

Abstract translation: 提供了一种系统和方法，用于使用从异步间隔时钟导出的抖动衰减时钟重新同步传输信号。 先进先出（FIFO）存储器接收从具有第一频率的第一时钟导出的异步间隔时钟。 间隔时钟的平均第二频率小于第一频率。 数据的输入串行流以响应于有间隙的时钟的速率加载。 对于有间隙的时钟进行迭代计算动态分子（DN）和动态分母（DD），得到平均分子（A和平均分母（AD）），第一个频率乘以AN / AD 创建具有第二频率的抖动衰减的第二时钟，FIFO存储器接受抖动衰减的第二时钟并以第二频率从存储器提供数据，成帧器接收来自FIFO存储器的数据和抖动衰减的第二时钟。

公开(公告)号：US08848686B1

公开(公告)日：2014-09-30

申请号：US13080888

申请日：2011-04-06

Applicant: Shi Cheng ,  Ravi Narasimhan

Inventor： Shi Cheng ,  Ravi Narasimhan

IPC: H04J3/06 ,  H04J11/00

CPC classification number: H04L5/0007 ,  H04L5/0048 ,  H04L25/0204 ,  H04L25/0228 ,  H04L25/03159 ,  H04L27/2636 ,  H04L27/2662 ,  H04L27/2695

Abstract: A system and method are provided for Single Carrier-Frequency-Division Multiple Access (SC-FDMA) Physical Uplink Control Channel (PUCCH) format 2/2a/2b detection. A receiver accepts a plurality of multicarrier signals transmitted simultaneously from a plurality of transmitters, with overlapping carrier frequencies. For each multicarrier signal, a single tap measurement of time delay is performed using a Direction of Arrival (DoA) technique. After performing a back-end processing operation, PUCCH 2/2a/2b format signals are detected. The back-end processing operation is selected from one of the following options: (1) decorrelation, channel estimation, equalization per user, and decoding per user; (2) channel estimation, equalization, and decoding per user; (3) decorrelation plus maximum likelihood detection (ML) per user; and, (4) ML detection over all users. Selection criteria is also provided.

Abstract translation: 提供了用于单载波 - 频分多址（SC-FDMA）物理上行链路控制信道（PUCCH）格式2 / 2a / 2b检测的系统和方法。 接收机接受多个发射机同时发射的多载波信号，具有重叠的载波频率。 对于每个多载波信号，使用到达方向（DoA）技术来执行时间延迟的单次测量。 在执行后端处理操作之后，检测到PUCCH2 / 2a / 2b格式信号。 后端处理操作从以下选项之一中选择：（1）去相关，信道估计，每个用户的均衡和每个用户的解码; （2）每个用户的信道估计，均衡和解码; （3）每个用户的去相关加最大似然检测（ML）; 和（4）对所有用户的ML检测。 还提供了选择标准。

公开(公告)号：US20140281275A1

公开(公告)日：2014-09-18

申请号：US13799268

申请日：2013-03-13

Applicant: David Alan Kruckemyer ,  John Gregory Favor

Inventor： David Alan Kruckemyer ,  John Gregory Favor

IPC: G06F12/08

CPC classification number: G06F12/0833 ,  G06F1/3243 ,  G06F2212/1028 ,  Y02D10/13

Abstract: Various aspects provide for implementing a cache coherence protocol. A system comprises at least one processing component and a centralized controller. The at least one processing component comprises a cache controller. The cache controller is configured to manage a cache memory associated with a processor. The centralized controller is configured to communicate with the cache controller based on a power state of the processor.

Abstract translation: 各个方面提供了实现高速缓存一致性协议。 系统包括至少一个处理部件和集中控制器。 所述至少一个处理组件包括高速缓存控制器。 高速缓存控制器被配置为管理与处理器相关联的高速缓冲存储器。 集中控制器被配置为基于处理器的功率状态与高速缓存控制器进行通信。

公开(公告)号：US20140266328A1

公开(公告)日：2014-09-18

申请号：US13846311

申请日：2013-03-18

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Yehuda AZENKOT ,  Michael GROSNER ,  Timothy P. WALKER

IPC: H03L7/16

CPC classification number: H03L7/06

Abstract: Systems and methods for frequency synthesis using a gapper. A frequency synthesizer may comprise a gapper, a first integer divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the first integer divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a gapped signal output from the first integer divider and attenuating jitter from the gapped signal.

Abstract translation: 使用缝隙器进行频率合成的系统和方法。 频率合成器可以包括间隔器，第一整数除法器和锁相环（PLL）。 当输出信号的频率意图大于相应的输入信号时，由第一整数除法器可以通过间隙借用一个因子，以便产生一个大于1的有理分频比G，以使分频器能够 通过G执行除法。PLL能够将从第一整数分频器输出的有间隙信号相乘并衰减来自有间隙信号的抖动。

公开(公告)号：US08838999B1

公开(公告)日：2014-09-16

申请号：US13109620

申请日：2011-05-17

Applicant: Satish Sathe ,  Sundeep Gupta

Inventor： Satish Sathe ,  Sundeep Gupta

IPC: H04L29/06

CPC classification number: H04L63/0428 ,  H04L47/52 ,  H04L69/16 ,  H04L69/22

Abstract: A system and method are provided for the cut-through encryption of packets transmitted via a plurality of input/output (IO) ports. A system-on-chip is provided with a first plurality of input first-in first out (FIFO) memories, an encryption processor, and a first plurality of output FIFOs, each associated with a corresponding input FIFO. Also provided is a first plurality of IO ports, each associated with a corresponding output FIFO. At a tail of each input FIFO, packets from the SoC are accepted at a corresponding input data rate. Packet blocks are supplied to the encryption processor, from a head of each input FIFO, in a cut-through manner. The encryption processor supplies encrypted packet blocks to a tail of corresponding output FIFOs. The encrypted packet blocks are transmitted from each output FIFO, via a corresponding IO port at a port speed rate effectively equal to the corresponding input data rate.

Abstract translation: 提供了一种用于对通过多个输入/输出（IO）端口传输的分组的直通加密的系统和方法。 片上系统设置有第一多个输入先进先出（FIFO）存储器，加密处理器和第一多个输出FIFO，每个与对应的输入FIFO相关联。 还提供了第一多个IO端口，每个IO端口与相应的输出FIFO相关联。 在每个输入FIFO的尾部，来自SoC的数据包以相应的输入数据速率被接受。 分组块以切入方式从每个输入FIFO的头部提供给加密处理器。 加密处理器将加密的分组块提供给相应的输出FIFO的尾部。 加密的分组块通过相应的IO端口从每个输出FIFO发送，端口速率有效地等于对应的输入数据速率。

公开(公告)号：US08792789B1

公开(公告)日：2014-07-29

申请号：US13413705

申请日：2012-03-07

Applicant: Badri Varadarajan ,  Daruish Dabiri ,  Subhash Roy

Inventor： Badri Varadarajan ,  Daruish Dabiri ,  Subhash Roy

IPC: H04B10/00 ,  H04B10/06

CPC classification number: H04B10/6161

Abstract: A method is provided for performing chromatic dispersion (CD) compensation. A zero-forcing filter is calculated with a number of taps (n) required to nullify a chromatic dispersion frequency response of an optical channel. The number of taps in the zero-forcing filter is truncated to a number equal to (n−x), where x is an integer greater than 0. In one aspect, the chromatic dispersion frequency response of the optical channel is partitioned into a plurality of constituent chromatic dispersion responses, and a zero-forcing filter is calculated for each of the plurality of constituent chromatic dispersion responses. The number of taps in each of the plurality of zero-forcing filters is truncated, and the CD compensation filter is formed for each of the plurality of truncated tap zero-forcing filters. In another aspect, the tap values of the zero-forcing filter are quantized to a finite quantization set.

Abstract translation: 提供了一种用于执行色散（CD）补偿的方法。 使用消除光通道的色散频率响应所需的抽头数（n）来计算零强制滤波器。 迫零滤波器中的抽头数被截断为等于（n-x）的数字，其中x是大于0的整数。在一个方面，光信道的色散频率响应被划分成多个 并且针对多个构成色散响应中的每一个计算零强迫滤波器。 多个迫零滤波器中的每一个中的抽头数量被截断，并且为多个截断的抽头强迫滤波器中的每一个形成CD补偿滤波器。 在另一方面，迫零滤波器的抽头值被量化为有限量化集。

公开(公告)号：US08772966B1

公开(公告)日：2014-07-08

申请号：US13110162

申请日：2011-05-18

Applicant: Abhishek Agrawal ,  Priyank Shukla

Inventor： Abhishek Agrawal ,  Priyank Shukla

IPC: H02J1/00 ,  H02J3/00

CPC classification number: H02J1/08 ,  H02J1/108 ,  Y10T307/696

Abstract: A power supply source selection circuit is provided with a comparator and a switch. The comparator has an input to accept a first reference voltage directly proportional to a bandgap reference voltage. For example, the bandgap voltage may be derived from a battery voltage. The comparator has an input to accept a second reference voltage directly proportional to a first supply voltage (e.g., a line voltage), and an output to supply a switch signal in response to comparing the second reference voltage to the first reference voltage. The switch has an input to accept the first supply voltage, an input to accept a second supply voltage, and input to accept the switch signal. The switch has an output to supply a third supply voltage to a regulator. The third voltage has a voltage potential less than or equal to a maximum voltage value. The switch selects between the first supply voltage and the second supply voltage in response to the switch signal.

Abstract translation: 电源选择电路设有比较器和开关。 比较器具有接收与带隙参考电压成正比的第一参考电压的输入。 例如，带隙电压可以从电池电压导出。 比较器具有输入以接受与第一电源电压（例如，线路电压）成正比的第二参考电压，以及响应于将第二参考电压与第一参考电压进行比较而提供开关信号的输出。 该开关具有接受第一电源电压的输入端，接受第二电源电压的输入端，并接受开关信号的输入。 该开关具有向调节器提供第三电源电压的输出。 第三电压具有小于或等于最大电压值的电压电位。 该开关响应于开关信号在第一电源电压和第二电源电压之间进行选择。