公开(公告)号：US20160234043A1

公开(公告)日：2016-08-11

申请号：US14619952

申请日：2015-02-11

Applicant: Applied Micro Circuits Corporation

Inventor： Yehuda AZENKOT ,  Guy Jacque FORTIER

IPC: H04L25/03 ,  H04L7/00

CPC classification number: H04L25/03019 ,  H04L7/0025 ,  H04L7/0062 ,  H04L2025/03592

Abstract: Systems and methods of mitigating precursor ISIs for communication channels having time-variant precursor channel responses using digital circuit designs. A phase adaptation circuit is utilized in a receiver and configured to generate a phase control signal responsive to an input signal and based on the current precursor channel response. The phase control signal controls the phase shift of a recovered clock to a position where the precursor ISI at h(−1) is minimized. The phase control signal corresponds to a “feed-forward equalization (FFE) first tap weight” obtained via a digital least-mean-square (LMS) process.

Abstract translation: 用于使用数字电路设计具有时变先驱信道响应的通信信道的前体ISI的系统和方法。 在接收机中使用相位自适应电路，并且被配置为响应于输入信号并且基于当前前置信道响应产生相位控制信号。 相位控制信号将恢复的时钟的相移控制在h（-1）处的前体ISI最小化的位置。 相位控制信号对应于通过数字最小均方（LMS）处理获得的“前馈均衡（FFE）第一抽头权重”。

公开(公告)号：US20140375364A1

公开(公告)日：2014-12-25

申请号：US14469456

申请日：2014-08-26

Applicant: Applied Micro Circuits Corporation

Inventor： Yehuda AZENKOT ,  Michael GROSNER ,  Timothy P. WALKER

IPC: H03L7/16

CPC classification number: H03L7/06

Abstract: Systems and methods for frequency synthesis using a gapper and a multi-modulus divider. A frequency synthesizer may comprise a gapper, a multi-modulus divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a gapped signal output from the first integer divider and attenuating jitter from the gapped signal.

Abstract translation: 使用间隙和多模式分频器进行频率合成的系统和方法。 频率合成器可以包括间隔器，多模式分频器和锁相环（PLL）。 当输出信号的频率意图大于相应的输入信号时，可以由分频器借由分频器的因子，以产生大于1的有理分频比G，以使分频器能够执行 由G.的分频。PLL能够乘以来自第一整数分频器的有间隙信号输出，并从有间隙信号衰减抖动。

公开(公告)号：US20140266339A1

公开(公告)日：2014-09-18

申请号：US13846171

申请日：2013-03-18

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Yehuda AZENKOT ,  Michael GROSNER ,  Timothy P. WALKER

IPC: H03L7/08

CPC classification number: H03L7/06

Abstract: Systems and methods for generating gapped signals comprising a Delta Sigma Modulator (DSM) configured to generate gapping control signals used to control gap removal rates of an associated gapping unit. The DSM is configured to generate a gapping control signal based on a value of an overflow resulted from performing adding a first number with a remainder of a stored value modulo a second number. The gap removal rates as well as the gap removal resolutions can be adjusted by selecting appropriate values of the first number, the stored value, and the second number. The gapping resolution can be a portion of a pulse. The first number and the second number may be derived from an intended frequency ratio between a gapped signal and a corresponding input signal. The gapping unit may comprise a gapping circuit or a multi-modulus divider.

Abstract translation: 用于产生有间隙信号的系统和方法包括配置成产生用于控制相关间隙单元的间隙去除速率的间隙控制信号的ΔΣ调制器（DSM）。 DSM被配置为基于通过执行将具有第二数量的存储值的剩余部分的第一数字相加的溢出的值来生成间隙控制信号。 可以通过选择第一个数字，存储值和第二个数字的适当值来调整间隙去除率以及间隙去除分辨率。 间隙分辨率可以是脉冲的一部分。 第一数字和第二数字可以从有间隙信号和对应的输入信号之间的预期频率比率导出。 间隙单元可以包括间隙电路或多模式分配器。

公开(公告)号：US20150110233A1

公开(公告)日：2015-04-23

申请号：US14061307

申请日：2013-10-23

Applicant: Applied Micro Circuits Corporation

Inventor： Yehuda AZENKOT ,  Timothy P. Walker

IPC: H04L7/033

CPC classification number: H03L7/093 ,  H04J3/07

Abstract: Systems and methods for efficient jitter mitigation or removal from a gapped signal. A phase mitigation module is employed to generate discrete correction values for modifying phase error signals detected between a gapped signal and a feedback signal of the PLL. The correction values can be digitally subtracted from the output of a phase frequency detector associated with the PLL. The sequence of correction values can be determined based on phase frequency differences between the input signal and a targeted feedback signal that is free of jitter and has a period equal to an average period of the input signal. An average of the correction values is substantially equal to zero, and an average of the modified phase error signal is substantially equal to zero.

Abstract translation: 用于有效抖动缓解或从间隙信号中移除的系统和方法。 使用相位缓解模块来产生离散校正值，用于修改在有效信号和PLL的反馈信号之间检测的相位误差信号。 可以从与PLL相关联的相位频率检测器的输出中数字地减去校正值。 校正值的顺序可以基于输入信号和无抖动的目标反馈信号之间的相位差，并且具有等于输入信号的平均周期的周期来确定。 校正值的平均值基本上等于零，并且修正的相位误差信号的平均值基本上等于零。

公开(公告)号：US20140314192A1

公开(公告)日：2014-10-23

申请号：US13865843

申请日：2013-04-18

Applicant: Applied Micro Circuits Corporation

Inventor： Yehuda AZENKOT ,  Timothy P. WALKER

IPC: H04L7/00 ,  H04L1/00

CPC classification number: H04L1/004 ,  H03L1/00 ,  H03L7/081 ,  H03L7/107 ,  H03L2207/50 ,  H04J3/076

Abstract: Systems and methods for smoothing jitter generated by byte stuffing. A frequency synthesizer comprises a smoothing logic coupled with a PLL. The smoothing logic is configured to modify a phase error signal generated by a phase frequency detector into a distributed phase error signal that spread over multiple clock cycles. The distributed phase error signal is used to drive a DCO. The smoothing logic may comprise a ramping logic operable to generate a series of ramping values to substitute a phase difference in the phase error signal. The phase difference may correspond to a stuffing byte.

Abstract translation: 用于平滑由字节填充产生的抖动的系统和方法。 频率合成器包括与PLL耦合的平滑逻辑。 平滑逻辑被配置为将由相位频率检测器产生的相位误差信号修改成在多个时钟周期上分布的分布相位误差信号。 分布相位误差信号用于驱动DCO。 平滑逻辑可以包括斜坡逻​​辑，其可操作以产生一系列斜坡值来代替相位误差信号中的相位差。 相位差可对应于填充字节。

公开(公告)号：US20180123776A1

公开(公告)日：2018-05-03

申请号：US15336435

申请日：2016-10-27

Applicant: Applied Micro Circuits Corporation

Inventor： Yehuda AZENKOT ,  Bart R. ZEYDEL

IPC: H04L7/04 ,  H04L25/08 ,  H04L12/26 ,  H04B17/336

CPC classification number: H04L7/04 ,  H04B17/336 ,  H04L7/0025 ,  H04L7/0029 ,  H04L7/0037 ,  H04L7/0062 ,  H04L25/0307 ,  H04L25/03885 ,  H04L25/08 ,  H04L27/01 ,  H04L43/028

Abstract: System and method of timing recovery for recovering a clock signal with reduced interference with clock phase correction by an adaptive equalizer. The equalizer in the timing recovery loop is dynamically adapted to the current channel characteristics that vary over time. The equalizer includes compensation logic operable to detect and compensate a correction of clock phase ascribed to the equalization adaptation. The compensation logic can calculate the offset between a center of filter (COF) value and a COF nominal value, the offset indicative of the amount and direction of clock phase correction contributed by the equalizer. Based on the offset, the compensation logic adjusts the equalized signal by adjusting the tap weights of the equalizer to correct the offset, thereby compensating the clock phase correction.

公开(公告)号：US20170373827A1

公开(公告)日：2017-12-28

申请号：US15191229

申请日：2016-06-23

Applicant: Applied Micro Circuits Corporation

Inventor： Yehuda AZENKOT ,  Bart R. ZEYDEL

IPC: H04L7/04 ,  H04L7/033 ,  H04L7/00

CPC classification number: H04L7/04 ,  H04L7/0062 ,  H04L7/0087 ,  H04L7/0331 ,  H04L25/03

Abstract: System and method of timing recovery for recovering a clock signal with reduced interaction between an adaptive channel estimator and the overall timing loop for correcting clock phase. The channel response estimation in the timing recovery loop is dynamically adapted to the current channel response that varies over time. The channel estimator includes compensation logic operable to detect and compensate a correction of clock phase ascribed to the channel estimator. The compensation logic can calculate the offset between a center of filter (COF) value and a COF nominal value, the offset indicative of the amount and direction of clock phase correction contributed by the channel estimator. Based on the offset, the compensation logic adjusts the estimates channel response by adjusting the tap weights of the channel estimator to correct the offset, thereby compensating the clock phase correction.

公开(公告)号：US20170331619A1

公开(公告)日：2017-11-16

申请号：US15151154

申请日：2016-05-10

Applicant: Applied Micro Circuits Corporation

Inventor： Yehuda AZENKOT ,  Bart R. ZEYDEL

IPC: H04L7/04 ,  H04L25/03 ,  H04L7/00 ,  H04L7/033

CPC classification number: H04L7/04 ,  H04L7/0062 ,  H04L7/0087 ,  H04L7/0331 ,  H04L25/024 ,  H04L25/03019 ,  H04L25/03261 ,  H04L25/03292 ,  H04L25/03949 ,  H04L2025/03592 ,  H04L2025/03636

Abstract: System and method of timing recovery for recovering a clock signal by using adaptive channel response estimation. The channel response estimation in the timing recovery loop is dynamically adapted to the current channel response that varies over time. More particularly, the channel estimation coefficients used in a channel estimator can be adapted based on an error signal representing the difference between a received signal at the timing recovery loop and an estimated signal output from a channel estimator. Further, to prevent undesirable interaction between the channel estimator and the overall timing recovery loop with respect to clock phase recovery, the adaptation of channel estimation can be controlled in terms of speed or time so as to reduce or eliminate the channel estimator's effect on clock phase correction.

公开(公告)号：US20170163380A1

公开(公告)日：2017-06-08

申请号：US14961228

申请日：2015-12-07

Applicant: Applied Micro Circuits Corporation

Inventor： Yehuda AZENKOT ,  Bart ZEYDEL

IPC: H04L1/00

CPC classification number: H04L1/0054 ,  H03M13/4107 ,  H03M13/6502

Abstract: System and method of comparing-selecting state metric values for high speed. Viterbi decoding. In an Add-Compare-Select (ACS) unit, a select-control signal is produced by Boolean operations on comparator decision signals and used to control a multiplexer structure. The comparator decision signals can be generated in parallel by an array of comparators comparing all possible pairs of a set of state metrics values. The Boolean operations are predefined through Boolean algebra that uses the decision signals as variables and complies with restriction imposed by the selection criteria, e.g., to select an minimum or maximum value of the set of state metrics values. The Boolean operations are performed by a logic module implemented using basic logic gates, such as AND, OR and NOT. As a result, the multiplexer structure that receives the set of input values can output the optimum value responsive to the select control signal.

公开(公告)号：US20140266328A1

公开(公告)日：2014-09-18

申请号：US13846311

申请日：2013-03-18

Applicant: APPLIED MICRO CIRCUITS CORPORATION

Inventor： Yehuda AZENKOT ,  Michael GROSNER ,  Timothy P. WALKER

IPC: H03L7/16

CPC classification number: H03L7/06

Abstract: Systems and methods for frequency synthesis using a gapper. A frequency synthesizer may comprise a gapper, a first integer divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the first integer divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a gapped signal output from the first integer divider and attenuating jitter from the gapped signal.

Abstract translation: 使用缝隙器进行频率合成的系统和方法。 频率合成器可以包括间隔器，第一整数除法器和锁相环（PLL）。 当输出信号的频率意图大于相应的输入信号时，由第一整数除法器可以通过间隙借用一个因子，以便产生一个大于1的有理分频比G，以使分频器能够 通过G执行除法。PLL能够将从第一整数分频器输出的有间隙信号相乘并衰减来自有间隙信号的抖动。