公开(公告)号：US20250113483A1

公开(公告)日：2025-04-03

申请号：US18479816

申请日：2023-10-02

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： ZAR LWIN ZIN ,  SHYUE SENG TAN ,  ENG HUAT TOH

IPC: H10B20/25

Abstract: The embodiments herein relate to antifuses capable of forming localized conductive links and methods of forming the same. An antifuse is provided. The antifuse includes a substrate, a dielectric liner, and an electrode. The substrate includes a conductor layer, and a trench is in the conductor layer. The trench includes a first conductor surface and a second conductor surface. The dielectric liner is in the trench. The electrode is on the dielectric liner in the trench, and the electrode includes a first electrode surface and a second electrode surface converging to the first electrode surface.

公开(公告)号：US12266702B2

公开(公告)日：2025-04-01

申请号：US17834982

申请日：2022-06-08

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Young Way Teh ,  Bin Zhu ,  Madhu Sudan Mukhopadhyay ,  Subramanian Sundareswara

IPC: H01L29/417 ,  H10B41/10 ,  H10B41/23 ,  H10B43/10 ,  H10B43/23 ,  H10D62/10 ,  H10D64/23

Abstract: Structures for a memory device and methods of forming a structure for a memory device. The structure includes a first and second source/drain regions in a semiconductor substrate, a first gate stack on the semiconductor substrate, and a second gate stack on the semiconductor substrate adjacent to the first gate stack. The first and second gate stacks are positioned in a lateral direction between the first source/drain region and the second source/drain region. The first gate stack includes first and second gate electrodes, and the first gate electrode includes segments spaced apart along a longitudinal axis of the first gate stack.

公开(公告)号：US12266671B2

公开(公告)日：2025-04-01

申请号：US17507213

申请日：2021-10-21

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eric Linardy ,  Eng Huat Toh ,  Ping Zheng ,  Kiok Boone Elgin Quek

IPC: H01L27/146 ,  H10F39/00 ,  H10F39/18

Abstract: Structures for a photodetector and methods of forming a structure for a photodetector. The structure includes a semiconductor layer having a p-n junction and a deep trench isolation region extending through the semiconductor layer. The deep trench isolation region includes first layers and second layers that alternate with the first layers to define a Bragg mirror. The first layers contain a first material having a first refractive index, and the second layers contain a second material having a second refractive index that is greater than the first refractive index.

公开(公告)号：US12265048B2

公开(公告)日：2025-04-01

申请号：US18058349

申请日：2022-11-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhuojie Wu

IPC: G01N27/22 ,  G02B6/12

Abstract: An integrated circuit (IC) structure includes a substrate; and a plurality of moisture sensors along an edge of an optical input/output (I/O) opening in the substrate. The plurality of moisture sensors are positioned between a primary guard ring and a moisture barrier. The moisture sensors may detect moisture in a sequential manner to monitor moisture ingress and predict when remedial action is necessary. The teachings of the disclosure may be applicable to any IC structure including an I/O opening, and in particular, IC structures that have elongated I/O openings such as photonic integrated structures (PICs) with optical I/O openings for photonics components, e.g., an optical fiber or an external laser. The moisture sensors provide an early and definitive alarm for moisture, with no false alarms. The system accurately predicts time to failure and allows adjustment based on real time field data input.

公开(公告)号：US12261215B2

公开(公告)日：2025-03-25

申请号：US17649184

申请日：2022-01-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Haiting Wang ,  Zhenyu Hu

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66

Abstract: A structure is provided, the structure may include an active layer arranged over a buried oxide layer, the active layer having a top surface. The top surface of the active layer may have a first portion and a second portion. A barrier stack may be arranged over the first portion of the top surface of the active layer. The barrier stack may include a barrier layer. The second portion of the top surface of the active layer may be adjacent to the barrier stack. A fin may be spaced from the first portion of the top surface of the active layer by the barrier stack, the fin having a first side surface, a second side surface opposite to the first side surface and a top surface. A dielectric layer may be arranged on the first side surface, the second side surface and the top surface of the fin, and the second portion of the top surface of the active layer. A metal layer may be arranged over the dielectric layer.

公开(公告)号：US12260163B2

公开(公告)日：2025-03-25

申请号：US17679178

申请日：2022-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Navneet Jain ,  Mahbub Rashed

IPC: G06F30/39 ,  G06F30/392 ,  G06F30/398 ,  G06F111/04 ,  G06F111/20

Abstract: Disclosed are embodiments of a computer-aided design system and corresponding method for power-optimized timing closure of an integrated circuit (IC) design. In the embodiments, a cell library includes sets of cells, where each cell in the same set has the same internal structure but different combinations of cell boundary isolation structures associated with different passive delay values. Timing closure includes replacement of a cell in a previously generated layout with another cell from the same set in order to adjust delay (e.g., increase delay) of a data signal or clock signal and, thereby facilitate fixing of a previously identified violation of a timing constraint. By eliminating or at least minimizing the need to insert buffer and/or inverter cells into a layout to add delay to a data signal and/or a clock signal during timing closure, the embodiments avoid or at least limit concurrent increases in power consumption and area consumption.

公开(公告)号：US12249959B1

公开(公告)日：2025-03-11

申请号：US18484504

申请日：2023-10-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Qiao Yang ,  Chi Zhang

IPC: H03B5/12 ,  H03B5/04 ,  H03B5/36

Abstract: Disclosed is a voltage-controlled oscillator (VCO) including at least an inductor-capacitor (LC) resonant circuit (including varactors that receive a variable input voltage), cross-coupled transistors connected to the LC resonant circuit, and an LC filter connected to a shared source node of the cross-coupled transistors. The cross-coupled transistors can have back gates connected to receive a variable back gate bias voltage (Vbg), which is dependent on Vin to ensure that an optimal relationship between the oscillating frequency (ω0) of the LC resonant circuit and the resonant frequency (ω1) of the LC filter is continuously maintained to minimize phase noise. For example, if Vin is increased to increase varactor capacitance and, thereby decrease ω0, then Vbg is also increased, thereby increasing the voltage (Vs-s) and the capacitance (Cs-s) on the shared source node connected to the LC filter, decreasing ω1, and maintaining an optimal relationship of ω0=ω1/2.

公开(公告)号：US20250079343A1

公开(公告)日：2025-03-06

申请号：US18240699

申请日：2023-08-31

Applicant: GlobalFoundries U.S. Inc.

Inventor： David Charles Pritchard ,  Ramesh Raghavan ,  Thirunavukkarasu Ranganathan ,  Rajesh Reddy Tummuru ,  Benoit Francois Claude Ramadout ,  Luca Pirro

IPC: H01L23/00 ,  H01L29/06 ,  H01L29/66

Abstract: Embodiments of the disclosure provide a structure and related method for a gate over semiconductor regions that are not aligned. Structures according to the disclosure include a first semiconductor region extending from a first widthwise end to a second widthwise end within a substrate. A second semiconductor region is adjacent the first semiconductor region and extends from a first widthwise end to a second widthwise end within the substrate. The second widthwise end of the second semiconductor region is non-aligned with the second widthwise end of the first semiconductor region. A gate structure is over the substrate and extends widthwise over the first semiconductor region and the second semiconductor region.

公开(公告)号：US20250078913A1

公开(公告)日：2025-03-06

申请号：US18459530

申请日：2023-09-01

Applicant: GlobalFoundries U.S. Inc.

Inventor： Xuemei Hui ,  Shafiullah Syed ,  Qiao Yang ,  Wei Zhao

IPC: G11C11/412 ,  G11C11/419 ,  H10B10/00

Abstract: A static random access memory (SRAM) cell includes P-type and N-type transistors having secondary gates. A node connected to all secondary gates receives a write enable signal (WEN). A low WEN forward biases the P-type transistors and increases the toggle threshold voltage (Vtth) of the SRAM cell to avoid data switching during a read. A high WEN forward biases the N-type transistors and decreases Vtth during a write. The SRAM cell can be implemented using a fully depleted semiconductor-on-insulator technology, where the secondary gates include corresponding portions of a well region below. In this case, an array of SRAM cells can be above a single well region. Alternatively, the array can be sectioned into sub-arrays above different well regions and a decoder can output sub-array-specific WENs to the different well regions (e.g., with only one WEN being high at a given time to reduce capacitance).

公开(公告)号：US20250076575A1

公开(公告)日：2025-03-06

申请号：US18241289

申请日：2023-09-01

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jae Kyu Cho ,  Norman Robson

IPC: G02B6/122 ,  G02B6/13 ,  H01L21/56 ,  H01L23/00 ,  H01L25/16

Abstract: Structures for a co-packaged photonics chip and electronic chip, and associated methods. The structure comprises a layer comprising a molding compound, an electronic chip and a photonics chip affixed in the layer, and a waveguiding structure including a waveguide core adjacent to the photonics chip. The photonics chip includes an optical coupler, the waveguide core includes a portion that overlaps with the optical coupler, and the waveguide core comprises a polymer.