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    High voltage MOSFET device with improved breakdown voltage
    22.
    发明授权
    High voltage MOSFET device with improved breakdown voltage 有权

    公开(公告)号：US12170329B2

    公开(公告)日：2024-12-17

    申请号：US17692218

    申请日：2022-03-11

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Anupam Dutta ,  Vvss Satyasuresh Choppalli ,  Rajendran Krishnasamy

    IPC: H01L29/78 ,  H01L21/3215 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66

    Abstract: According to various embodiments, there is provided a MOSFET device. The MOSFET device may include a substrate; a first doped region disposed in the substrate; a second doped region disposed in the substrate, wherein the first doped region and the second doped region are laterally adjacent to each other; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a gate disposed on the substrate, over the first and second doped regions, and between the third and fourth doped regions; and at least one high resistance region embedded in at least the second doped region, wherein the first doped region has a first conductivity type, wherein the second doped region, the third doped region, and the fourth doped region have a second conductivity type, wherein the first conductivity type and the second conductivity type are different.

    REFLECTORS FOR A PHOTONICS CHIP
    25.
    发明申请
    REFLECTORS FOR A PHOTONICS CHIP 有权

    公开(公告)号：US20240402426A1

    公开(公告)日：2024-12-05

    申请号：US18203321

    申请日：2023-05-30

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Yusheng Bian ,  Ryan Sporer ,  Karen Nummy

    IPC: G02B6/124 ,  G02B6/13

    Abstract: Structures for a photonics chip that include a reflector and methods of forming such structures. The structure comprises a reflector including a dielectric layer on a semiconductor substrate, a plurality of trenches in the dielectric layer, and a reflector layer. Each trench includes a plurality of sidewalls, and the reflector layer includes a portion on the sidewalls of each trench. The structure further comprises a photonic component over the reflector.

    LATERAL BIPOLAR TRANSISTORS
    27.
    发明公开
    LATERAL BIPOLAR TRANSISTORS 审中-公开

    公开(公告)号：US20240363741A1

    公开(公告)日：2024-10-31

    申请号：US18767418

    申请日：2024-07-09

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Jagar SINGH

    IPC: H01L29/735 ,  H01L29/08 ,  H01L29/10

    CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: an emitter in a semiconductor substrate; a collector in the semiconductor substrate; a base contact region in the semiconductor substrate and adjacent to the collector and the emitter; and a shallow trench isolation structure overlapping the base contact region and separating the base contact region from the emitter and the collector.

    Semiconductor structure with semiconductor-on-insulator region and method
    29.
    发明授权
    Semiconductor structure with semiconductor-on-insulator region and method 有权

    公开(公告)号：US12131904B2

    公开(公告)日：2024-10-29

    申请号：US17934220

    申请日：2022-09-22

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Ramsey Hazbun ,  Alvin J. Joseph ,  Siva P. Adusumilli ,  Cameron Luce

    IPC: H01L21/02

    CPC classification number: H01L21/02433 ,  H01L21/02381 ,  H01L21/02639 ,  H01L21/02647

    Abstract: Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer. Depending upon the embodiments, different process steps are further performed to form plugs in at least the upper portions of the openings and insulators (including dielectric layers and/or a pocket of trapped air, of trapped gas or under vacuum) in the cavities.

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