公开(公告)号：US20080020565A1

公开(公告)日：2008-01-24

申请号：US11539614

申请日：2006-10-06

申请人： Fan Tseng ,  Chi Wu ,  Wei Chien

发明人： Fan Tseng ,  Chi Wu ,  Wei Chien

IPC分类号： H01L21/44 ,  G03F1/00

CPC分类号： H01L21/76807 ,  G03F1/50 ,  G03F1/54 ,  H01L2221/1021

摘要： A method for creating a dual damascene structure while using only one lithography and masking step. Conventional dual damascene structures utilize two lithography steps: one to mask and expose the via, and a second step to mask and expose the trench interconnection. The novel method for creating a dual damascene structure allows for a smaller number of processing steps, thus reducing the processing time needed to complete the dual damascene structure. In addition, a lower number of masks may be needed. The exemplary mask or reticle used within the process incorporates different regions possessing different transmission rates. During the exposing step, light from an exposing source passes through the mask to expose a portion of the photoresist layer on top of the wafer. Depending on the transmission rate of the different regions, different thickness of the photoresist layer are exposed and later removed by a developing solution, which allows a subsequent etch process to remove portions of both the dielectric layer and photoresist layer to create a dual damascene structure.

摘要翻译： 一种用于仅使用一个光刻和掩蔽步骤来创建双镶嵌结构的方法。 传统的双镶嵌结构使用两个光刻步骤：一个用于掩蔽和暴露通孔，以及第二步骤，以掩蔽和暴露沟槽互连。 用于创建双镶嵌结构的新颖方法允许较少数量的处理步骤，从而减少完成双镶嵌结构所需的处理时间。 此外，可能需要较少数量的掩模。 在该过程中使用的示例性掩模或掩模版包含具有不同透射率的不同区域。 在曝光步骤期间，来自曝光源的光穿过掩模以暴露晶片顶部上的光致抗蚀剂层的一部分。 取决于不同区域的透射率，曝光不同厚度的光致抗蚀剂层，随后通过显影液去除，这使得随后的蚀刻工艺能够去除介电层和光致抗蚀剂层的部分以产生双镶嵌结构。

公开(公告)号：US20060141773A1

公开(公告)日：2006-06-29

申请号：US11321119

申请日：2005-12-28

申请人： Yung Kim

发明人： Yung Kim

IPC分类号： H01L21/4763

CPC分类号： H01L21/76807 ,  H01L21/31144 ,  H01L2221/1021

摘要： A method of forming a metal line in a semiconductor device reduces production costs through a simplified fabricating process. The method includes steps of forming a first metal line on a semiconductor substrate; forming an insulating layer over the semiconductor substrate including the first metal line; coating a photoresist on the insulating layer; aligning a diffraction mask having regions or patterns differing from each other in transmittance over the photoresist; patterning the photoresist by exposure and development using the diffraction mask to form a patterned photoresist having regions that differ in thickness; forming a via hole and a trench by etching the patterned photoresist and the insulating layer simultaneously to expose a prescribed portion of the first metal line; removing the remaining photoresist; and forming a second metal line and a contact in the trench and the via hole.

摘要翻译： 在半导体器件中形成金属线的方法通过简化的制造工艺降低了生产成本。 该方法包括以下步骤：在半导体衬底上形成第一金属线; 在包括第一金属线的半导体衬底上形成绝缘层; 在绝缘层上涂覆光致抗蚀剂; 对准具有在光致抗蚀剂上的透射率彼此不同的区域或图案的衍射掩模; 通过使用衍射掩模的曝光和显影来图案化光致抗蚀剂以形成具有不同厚度区域的图案化光致抗蚀剂; 通过同时蚀刻图案化的光致抗蚀剂和绝缘层来形成通孔和沟槽，以暴露第一金属线的规定部分; 去除剩余的光致抗蚀剂; 以及在沟槽和通孔中形成第二金属线和接触件。

公开(公告)号：US20040224261A1

公开(公告)日：2004-11-11

申请号：US10434614

申请日：2003-05-08

发明人： Douglas J. Resnick ,  Scott D. Hector ,  Richard D. Peters

IPC分类号： B05D003/00

CPC分类号： H01L21/76817 ,  H01L21/76807 ,  H01L2221/1021

摘要： An exemplary method for using multi-tiered templates with imprint lithography for producing dual damascene features is disclosed as comprising the steps of inter alia: positioning (step 150) a multi-tiered lithographic template (130) in contact with a resist layer (120); applying pressure to the template (130) so that the resist material (120) flows into the relief pattern of the template (130) thereby forming a patterned resist layer (125); optionally curing the patterned resist layer (125); removing (step 160) the template (130) from the patterned resist layer (125); and etching (steps 170, 180) the patterned resist layer (125) to develop a via-and-trench pattern in the patterning layer (117). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize the fabrication of dual damascene or other multi-tiered structures.

摘要翻译： 公开了一种用于使用具有压印光刻术的多层模板以产生双镶嵌特征的示例性方法，其包括以下步骤：特别地：定位（步骤150）与抗蚀剂层（120）接触的多层光刻模板（130） ; 向模板（130）施加压力，使得抗蚀剂材料（120）流入模板（130）的浮雕图案，从而形成图案化的抗蚀剂层（125）; 任选地固化图案化的抗蚀剂层（125）; 从图案化的抗蚀剂层（125）去除（步骤160）模板（130）; 以及蚀刻（步骤170,180）图案化的抗蚀剂层（125）以在图案形成层（117）中形成通孔和沟槽图案。 公开的特征和规格可以被不同地控制，配置，适配或以其他方式任意地修改，以进一步改进或以其他方式优化双镶嵌或其它多层结构的制造。

公开(公告)号：US06514857B1

公开(公告)日：2003-02-04

申请号：US09788164

申请日：2001-02-16

申请人： Mehul B. Naik ,  Tim Weidman ,  Dian Sugiarto ,  Allen Zhao

发明人： Mehul B. Naik ,  Tim Weidman ,  Dian Sugiarto ,  Allen Zhao

IPC分类号： H01L214763

CPC分类号： H01L21/31144 ,  H01L21/0212 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/0332 ,  H01L21/3121 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76829 ,  H01L21/76835 ,  H01L2221/1021 ,  Y10S438/942

摘要： A damascene structure, and a method of fabricating same, containing relatively low dielectric constant materials (e.g., k less than 3.8). A silicon-based, photosensitive material, such as plasma polymerized methylsilane (PPMS), is used to form both single and dual damascene structures containing low k materials. During the manufacturing process that forms the damascene structures, the silicon-based photosensitive material is used as both a hard mask and/or an etch stop.

公开(公告)号：US20020081531A1

公开(公告)日：2002-06-27

申请号：US09750853

申请日：2000-12-27

发明人： Ajay Jain

IPC分类号： G03F007/00

CPC分类号： H01L21/31144 ,  H01L21/76813 ,  H01L23/53238 ,  H01L2221/1021 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method comprising introducing a photoimageable material on a substrate; developing the photoimageable material over an opening area, the photoimageable material over a first portion of the opening area developed to a first extent and the photoimageable material over a second portion of the opening area developed to a different second extent; removing developed photoimageable material from the opening area; and forming an opening in the substrate in the opening area.

摘要翻译： 一种方法，包括在基底上引入可光成像的材料; 在开口区域上显影所述可光成像材料，所述可光成像材料在所述开口区域的第一部分上形成为第一程度，并且所述可光成象材料在所述开口区域的第二部分上形成为不同的第二程度; 从开口区域移除显影的可光成像材料; 以及在所述开口区域中在所述基板中形成开口。

公开(公告)号：US20020009675A1

公开(公告)日：2002-01-24

申请号：US09943995

申请日：2001-08-30

发明人： Nanseng Jeng ,  Christophe Pierrat

IPC分类号： G03F007/26

CPC分类号： G03F1/26 ,  G03F1/29 ,  G03F1/32 ,  G03F7/2022 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/76813 ,  H01L2221/1021

摘要： A method for forming a photomask including applying photoresist to a semiconductor substrate, exposing a first area of the photoresist to a first dosage of radiation, and exposing a second area of the photoresist to a second dosage of radiation. The first and second areas may be concurrently exposed. First and second regions of the photoresist are then removed to form first and second openings that have different depths in the photoresist. Such removal may be effected by developing the first and second areas of the photoresist. One of the openings may extend down to an insulating layer formed on the semiconductor substrate. A contact and/or trench etch may be performed to remove a portion of the insulating layer. Conductive material may then be deposited in the opening so formed to form a contact, a via, or another electrically conductive element that communicates with a structure underlying the insulating layer.

摘要翻译： 一种用于形成光掩模的方法，包括将光致抗蚀剂施加到半导体衬底，将所述光致抗蚀剂的第一区域暴露于第一剂量的辐射，以及将所述光致抗蚀剂的第二区域暴露于第二剂量的辐射。 第一和第二区域可以同时暴露。 然后去除光致抗蚀剂的第一和第二区域以形成在光致抗蚀剂中具有不同深度的第一和第二开口。 可以通过显影光致抗蚀剂的第一和第二区域来实现这种去除。 一个开口可以向下延伸到形成在半导体衬底上的绝缘层。 可以执行接触和/或沟槽蚀刻以去除绝缘层的一部分。 然后可以将导电材料沉积在如此形成的开口中以形成与绝缘层下方的结构连通的接触件，通孔或另一导电元件。

公开(公告)号：US06174801B1

公开(公告)日：2001-01-16

申请号：US09261997

申请日：1999-03-05

申请人： San-De Tzu ,  Ching-Shiun Chiu ,  Chia-Hui Lin

发明人： San-De Tzu ,  Ching-Shiun Chiu ,  Chia-Hui Lin

IPC分类号： H01L214763

CPC分类号： H01L21/76807 ,  G03F7/2059 ,  H01L21/02063 ,  H01L21/0277 ,  H01L21/3081 ,  H01L21/3086 ,  H01L2221/1021

摘要： A method is disclosed for employing direct electron beam writing in the lithography used for forming step-profiles in semiconductor devices. The number of steps in the profiles are not limited. An electron beam sensitive resist is formed over a substrate. The resist is then exposed to a scanning electron beam having precise information, including proximity effect correction data, to directly form stair-case-like openings in the resist. The highly accurately dimensioned step-profiles are then transferred into the underlying layers by performing appropriate etchings. The resulting structures are shown to be especially suitable for forming damascene interconnects for submicron technologies.

摘要翻译： 公开了一种在用于在半导体器件中形成阶梯轮廓的光刻中采用直接电子束写入的方法。 配置文件中的步骤数不受限制。 在衬底上形成电子束敏感抗蚀剂。 然后将抗蚀剂暴露于具有精确信息的扫描电子束，包括邻近效应校正数据，以直接在抗蚀剂中形成阶梯状开口。 然后通过执行适当的蚀刻将高度精确尺寸的阶梯轮廓转移到下面的层中。 所得到的结构显示出特别适用于形成亚微米技术的镶嵌互连。

公开(公告)号：US6156460A

公开(公告)日：2000-12-05

申请号：US10136

申请日：1998-01-21

申请人： Chao-Yuan Huang

发明人： Chao-Yuan Huang

IPC分类号： G03F1/00 ,  H01L21/768 ,  G03F9/00

CPC分类号： G03F1/50 ,  H01L21/76807 ,  H01L2221/1021

摘要： A photo-mask and a method of fabricating the same. A photo-mask comprises a quartz glass substrate, on which a clear area, a grey area, and a dark area formed over the quartz glass substrate. Incident light penetrates through the clear area completely, but only part of the incident light will go through the grey area since the other part of the incident light is absorbed by the grey area, On the other hand, incident light is blocked by the dark area completely.

摘要翻译： 光掩模及其制造方法。 光掩模包括石英玻璃基板，石英玻璃基板上形成有透明区域，灰色区域和暗区域。 入射光完全透过透明区域，但入射光的另一部分被灰色区域吸收，只有部分入射光将穿过灰色区域。另一方面，入射光被黑暗区域遮挡 完全

公开(公告)号：US6093508A

公开(公告)日：2000-07-25

申请号：US226765

申请日：1999-01-06

申请人： William J. Cote

发明人： William J. Cote

IPC分类号： G03F7/00 ,  G03F7/20 ,  G03F7/38 ,  G03F7/40 ,  H01L21/027 ,  H01L21/768

CPC分类号： H01L21/0274 ,  G03F7/0035 ,  G03F7/2022 ,  G03F7/38 ,  G03F7/405 ,  H01L21/76813 ,  H01L2221/1021

摘要： The present invention is embodied in a process for creating a dual damascene structure. The process includes the steps of forming a photoresist film on a substrate, pattern exposing the photoresist film to form a first pattern in the photoresist film, and forming an etch resistant layer in the first pattern. The resistant layer is resistant to a further pattern exposure and etching. The photoresist film is pattern exposed a second time to form a second pattern in the photoresist film. The sections of the photoresist film corresponding to the second pattern are removed and the substrate is etched to form the second pattern in the substrate. The resistant layer is removed and the substrate is etched to form the first pattern in the substrate. Finally, the remaining photoresist film is removed from the substrate.

摘要翻译： 本发明体现在一种创建双镶嵌结构的方法中。 该方法包括以下步骤：在衬底上形成光致抗蚀剂膜，图案曝光光致抗蚀剂膜以在光致抗蚀剂膜中形成第一图案，并在第一图案中形成耐蚀刻层。 电阻层可耐受进一步的图案曝光和蚀刻。 光致抗蚀剂膜第二次图案曝光以在光致抗蚀剂膜中形成第二图案。 去除对应于第二图案的光致抗蚀剂膜的部分，并且蚀刻衬底以在衬底中形成第二图案。 去除电阻层并蚀刻衬底以在衬底中形成第一图案。 最后，剩余的光致抗蚀剂膜从基板上去除。

公开(公告)号：US6066569A

公开(公告)日：2000-05-23

申请号：US940895

申请日：1997-09-30

申请人： Dirk Tobben

发明人： Dirk Tobben

IPC分类号： H01L21/3205 ,  H01L21/311 ,  H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/31144 ,  H01L21/76813 ,  H01L2221/1021

摘要： A process for the manufacture of silicon integrated circuits uses a dual damascene metallization process with an organic intermetal dielectric (14). A pattern to be etched is first etched in a hard mask (16) without exposing the underlying intermetal dielectric (14) and then transferred into the intermetal dielectric (14) on an enlarged scale.y

摘要翻译： 用于制造硅集成电路的方法使用具有有机金属间电介质的双镶嵌金属化工艺（14）。 要蚀刻的图案首先在硬掩模（16）中蚀刻，而不暴露下面的金属间电介质（14），然后以放大的尺度转移到金属间电介质（14）中。