公开(公告)号：US4441063A

公开(公告)日：1984-04-03

申请号：US147415

申请日：1980-05-06

Applicant: Richard W. Roof ,  Kenneth S. Berton

Inventor： Richard W. Roof ,  Kenneth S. Berton

IPC: G05F5/00 ,  H02M1/084 ,  H02M5/02 ,  H03K5/153 ,  H03K19/08 ,  H02P7/42

CPC classification number: H02M1/0845

Abstract: A pulse generating system for providing firing pulses to selectively trigger solid state control devices connected to a three-phase A.C. line system, and more specifically to trigger said devices in selected relation with respect to the phase and frequency of the A.C. line.

Abstract translation: 一种用于提供点火脉冲以选择性地触发连接到三相交流线系统的固态控制装置的脉冲发生系统，更具体地，涉及相对于交流线的相位和频率选择的关系触发所述装置。

公开(公告)号：US4347562A

公开(公告)日：1982-08-31

申请号：US161896

申请日：1980-06-23

Applicant: James H. Galloway

Inventor： James H. Galloway

IPC: H02M1/08 ,  H02M1/084 ,  H02M7/162 ,  H02P13/26

CPC classification number: H02M7/1626 ,  H02M1/0845

Abstract: A trigger system and method for use in a line commutated power converter as used in either a rectification or an inversion mode of operation and more particularly a trigger system and method for a static converter for accurately controlling the firing angles for controlled rectifiers for converting between multiphase a-c power and d-c power by use of digital signal having magnitudes which are varied for varying firing angles for providing a converted output having a regulated voltage and/or current.

Abstract translation: 一种用于线性换向功率转换器的触发系统和方法，其用于整流或反相操作模式，更具体地涉及一种用于精确控制受控整流器的触发角度的触发系统和方法，用于在多相 通过使用具有为改变触发角度而变化的量值的数字信号提供具有调节电压和/或电流的转换输出的交流电力和直流电力。

公开(公告)号：US4313061A

公开(公告)日：1982-01-26

申请号：US20134

申请日：1979-03-13

Applicant: Donald G. Thomas

Inventor： Donald G. Thomas

IPC: H02J3/12 ,  H02J3/14 ,  H02M1/084 ,  H02J5/00 ,  H02M7/155

CPC classification number: H02J3/14 ,  H02M1/0845 ,  Y02B70/3225 ,  Y04S20/222 ,  Y10T307/414 ,  Y10T307/484 ,  Y10T307/76

Abstract: A method and circuit as disclosed herein for varying the current to N electrical loads by the use of SCR's, the arrangement being such that the total current is sinusoidal and of uniform amplitude at a particular setting. The technique involves the steps of generating a load sequence waveform, the period of which is nN full cycles of the ac source where n is any positive integer, and, during each period of the waveform, generating a load firing pattern for initiating the flow of a current I in each load, the load pattern being such that (a) the currents in each of the loads are initiated at instants which are n full cycles of the ac source apart, and (b) maintaining the current in each load for d full cycles of the ac source, where d is a duty factor and is any positive integer equal to or greater than n, but less than or equal to nN, whereby the total current drawn from the ac source is uniform and equal to dI/n.

Abstract translation: 如本文所公开的用于通过使用SCR来改变电流到N个电负载的方法和电路，该布置使得总电流是正弦的并且在特定设置下具有均匀的幅度。 该技术涉及产生负载序列波形的步骤，其周期是交流电源的nN个整周期，其中n是任何正整数，并且在波形的每个周期期间，产生用于启动流量的负载点火模式 在每个负载中的电流I，负载模式使得（a）每个负载中的电流在交流电源的n个整周期的时刻启动，并且（b）将每个负载中的电流保持为d 交流源的全周期，其中d是占空系数，并且是等于或大于n但小于或等于nN的任何正整数，由此从ac源引出的总电流是均匀的并且等于dI / n 。

公开(公告)号：US4267570A

公开(公告)日：1981-05-12

申请号：US62304

申请日：1979-07-31

Applicant: Rudiger Braun

Inventor： Rudiger Braun

IPC: H02M1/084 ,  H02M7/515

CPC classification number: H02M7/5155 ,  H02M1/0845

Abstract: A digital control unit has an oscillator driven, binary coded counter, the outputs of which are connected to the first addend inputs of a number of adders. The second addend inputs of the adders are connected to phase angle inputs. The summation outputs of the adders are connected to a logic circuit, which derives timing pulses from the signals at the summation outputs of the adders and interlinks them to form a three-phase system of firing pulses for the controlled valves of the converter. The control unit can be used for fast shutdown of the controlled converter by blocking the firing pulses for the controlled main valves and shifting the firing pulses for the quenching valves as a function of the instantaneous phase of the converter output voltage; also the operating frequency can be increased.

Abstract translation: 数字控制单元具有振荡器驱动的二进制编码计数器，其输出连接到多个加法器的第一加数输入。 加法器的第二个加法输入连接到相位角输入。 加法器的求和输出连接到逻辑电路，该逻辑电路从加法器的求和输出处的信号中导出定时脉冲，并将它们互相连接，以形成用于转换器的受控阀的点火脉冲的三相系统。 控制单元可用于通过阻塞受控主阀的点火脉冲和作为转换器输出电压的瞬时相位的方式移动用于淬火阀的点火脉冲来快速关闭受控转换器; 也可以提高工作频率。

公开(公告)号：US4245292A

公开(公告)日：1981-01-13

申请号：US934052

申请日：1978-08-15

Applicant: Anatoly Y. Kalinichenko ,  Viktor I. Kirillov ,  Aron A. Rabinovich ,  Vladimir V. Maleev ,  Vagiz S. Sakaev

Inventor： Anatoly Y. Kalinichenko ,  Viktor I. Kirillov ,  Aron A. Rabinovich ,  Vladimir V. Maleev ,  Vagiz S. Sakaev

IPC: H02M1/084 ,  H02M3/139 ,  H02P13/24

CPC classification number: H02M1/0845 ,  H02M3/139

Abstract: A method of digital control of m-phase thyristor-pulse converters, in which the duration of the conductive state of the thyristors of each phase of an m-phase thyristor-pulse converter is changed by sending time-shifted and time-constant pulse trains successively from each control channel to the thyristors of respective phases with simultaneous shift of the onset of operation of the thyristors of each phase by (1/m) period of switching the thyristors. Successive connection of each control channel to a respective phase is effected upon achieving the maximum value of the control zone of each control channel. The apparatus for carrying out the proposed method includes a master oscillator connected to a clock counter whose outputs are connected to the inputs of a decoder for decoding the time-constant pulse trains and to the logic inputs of "m" decoders for decoding the time-shifted pulse trains. The data inputs of each of the "m" decoders are connected to the data outputs of a bidirectional counter connected to a control unit, while the ouput of each of the "m" decoders is connected to one of the "m" data inputs of a matching unit whose control inputs are connected to the control outputs of the bidirectional counter. The matching unit includes "m" groups of AND gates, each group comprising "m" AND gates; the output of each AND gate of the 1-th group is connected to the 1-th control output of the bidirectional counter, while the other input of the 1-th AND gate of each group is connected to the output of the decoder for decoding the 1-th time-shifted pulse train, where 1=1,2, . . . m and m is the number of phases of the polyphase thyristor-pulse d-c converter.

Abstract translation: 一种m相晶闸管脉冲转换器的数字控制方法，其中通过发送时移和时间常数脉冲串来改变m相晶闸管脉冲转换器各相的晶闸管导通状态的持续时间 从每个控制通道连续施加到各相的晶闸管，同时将每相的晶闸管的操作开始同时移动（1 / m）开关晶闸管的周期。 通过实现每个控制信道的控制区域的最大值来实现每个控制信道到相应相位的连续连接。 用于执行所提出的方法的装置包括连接到时钟计数器的主振荡器，其输出连接到用于对时间常数脉冲串进行解码的解码器的输入端以及与“m”个解码器的逻辑输入端进行解码， 移位脉冲列。 每个“m”个解码器的数据输入连接到连接到控制单元的双向计数器的数据输出，而每个“m”个解码器的输出连接到“m”个解码器的“m”个数据输入 匹配单元，其控制输入连接到双向计数器的控制输出。 匹配单元包括“m”个与门组，每组包括“m”与门; 第1组的每个与门的输出连接到双向计数器的第1个控制输出，而每组的第1个与门的另一个输入端连接到解码器的输出端用于解码 第1个时移脉冲序列，其中1 = 1,2。 。 。 m和m是多相晶闸管脉冲d-c转换器的相数。

公开(公告)号：US4208707A

公开(公告)日：1980-06-17

申请号：US871957

申请日：1978-01-24

Applicant: Mikhail V. Olshvang ,  Grigory M. Tsfasman ,  Alexei A. Sheremet

Inventor： Mikhail V. Olshvang ,  Grigory M. Tsfasman ,  Alexei A. Sheremet

IPC: H02M1/084 ,  H02M7/00

CPC classification number: H02M1/0845

Abstract: A method for control of a static valve converter consists of determining the difference between the actual and desired control pulse phases by the use of an equidistant pulse sequence, the frequency of which being equal to the coversion frequency, the pulse sequence phase being selected so that the mean difference between the equidistant pulse phase and the phase of the respective control pulses of all valves is equal to zero, and the pulse phase difference being determined for each individual valve. A control pulse automatic balancing unit incorporated in an apparatus for realizing the method of the present invention comprises an equidistant pulse sequence assembly, a shaping element, correcting signal circuits and logical AND elements equal in number to the number of conversion phases, and also logical circuits equal in number to the number of coversion phases. Each logical circuit comprises two logical AND elements, and a logical OR element connected to the outputs of the AND elements.

Abstract translation: 用于控制静态阀转换器的方法包括通过使用等距脉冲序列来确定实际和期望的控制脉冲相位之间的差异，等距脉冲序列的频率等于转换频率，脉冲序列相位被选择使得 所有阀的等距脉冲相位和相应控制脉冲的相位之间的平均差等于零，并且为每个单独的阀确定脉冲相位差。 结合在实现本发明的方法的装置中的控制脉冲自动平衡单元包括等距脉冲序列组件，整形元件，校正信号电路和与转换相位数相等的逻辑与元件，以及逻辑电路 数量相当于转化阶段的数量。 每个逻辑电路包括两个逻辑AND元素，以及连接到AND元件的输出的逻辑OR元件。

公开(公告)号：US3735241A

公开(公告)日：1973-05-22

申请号：US3735241D

申请日：1971-12-28

Applicant: ENGINEERING INC T

Inventor： O SULLIVAN G

IPC: G05F1/445 ,  H02M1/084 ,  G05F1/44

CPC classification number: H02M1/0845 ,  G05F1/445

Abstract: A polyphase digital controller comprised of circuitry to generate and count a group of digital clock pulses with the first pulse being counted after the zero crossing of the primary voltage. The number of pulses in the group is proportional to the control function representing (SCR) silicon controlled rectifiers off time. These clock pulses are counted by an up counter which is used to set an individual down counter in each phase. The up counter operates six times during each 360* of the input line. This setting of the down counters occurs when the primary voltage associated with the individual phase of each counter crosses zero. This zero crossing also starts the down counter associated with that phase, counting a clock frequency that is one-third the frequency of the up counter clock. When the down counter reaches zero it supplies a signal to fire the SCR controlling that phase.

Abstract translation: 多相数字控制器包括用于产生和计数一组数字时钟脉冲的电路，其中第一脉冲在初级电压过零之后被计数。 组中的脉冲数与表示（SCR）硅控制整流器关断时间的控制功能成比例。 这些时钟脉冲由向上计数器计数，该计数器用于在每个相位中设置单个递减计数器。 输入线每360度输出一次上升计数器。 当与每个计数器的各个相位相关联的主电压跨越零时，会产生向下计数器的设置。 该零交叉也启动与该相位相关联的向下计数器，对时钟频率进行计数，该时钟频率是向上计数器时钟频率的三分之一。 当向下计数器达到零时，它提供一个信号来触发控制该相位的SCR。

公开(公告)号：US20240333173A1

公开(公告)日：2024-10-03

申请号：US18623734

申请日：2024-04-01

Applicant: Inertech IP LLC

Inventor： Subrata K Mondal

IPC: H02M7/487 ,  H02J9/06 ,  H02M1/084 ,  H02M3/04 ,  H02M7/483 ,  H02M7/49 ,  H02M7/5387

CPC classification number: H02M7/487 ,  H02J9/061 ,  H02M3/04 ,  H02M1/0845 ,  H02M7/4835 ,  H02M7/49 ,  H02M7/53873 ,  H02M7/53875 ,  H02M7/53876

Abstract: Control systems for a multi-level diode-clamped inverter and corresponding methods include a processor and a digital logic circuit forming a hybrid controller. The processor identifies sector and region locations based on a sampled reference voltage vector V* and angle θe*. The processor then selects predefined switching sequences and pre-calculated turn-on time values based on the identified sector and region locations. The digital logic circuit generates PWM switching signals for driving power transistors of a multi-level diode-clamped inverter based on the turn-on time values and the selected switching sequences. The control system takes care of the existing capacitor voltage balancing issues of multi-level diode-clamped inverters while supplying both active and reactive power to an IT load. Using the control system, one can generate a symmetrical PWM signal that fully covers the linear under-modulation region.

公开(公告)号：US20240333137A1

公开(公告)日：2024-10-03

申请号：US18621208

申请日：2024-03-29

Applicant: SEIKO EPSON CORPORATION

Inventor： Shinji OZAKI

IPC: H02M1/32 ,  H02M1/084

CPC classification number: H02M1/32 ,  H02M1/0845

Abstract: There is provided a distributed control device including a sub-control circuit operated by using a power supply voltage, a first drive device controlled by the sub-control circuit, a first minor error output circuit that outputs a first minor error signal including first minor error information to the first drive device, a first major error output circuit that outputs a first major error signal including first major error information to the first drive device, a management control circuit that holds minor error information corresponding to the first minor error information and major error information corresponding to the first major error information, and a switching circuit that switches whether or not to supply the power supply voltage to the sub-control circuit. The switching circuit stops the supply of the power supply voltage to the sub-control circuit in accordance with the major error information.

公开(公告)号：US20240297571A1

公开(公告)日：2024-09-05

申请号：US18591469

申请日：2024-02-29

Applicant: Renesas Electronics America Inc.

Inventor： John Stuart KLEINE ,  Yashovardhan Rao POTLAPALLI ,  Michael Jason HOUSTON

IPC: H02M1/084 ,  H02M1/00 ,  H02M3/158

CPC classification number: H02M1/0845 ,  H02M1/0025 ,  H02M3/1586

Abstract: System and methods for a power converter are described. A controller can generate first clock signals and generate pulse width modulation (PWM) signals using the first clock signals to operate a first number of active phases in a power converter to supply power to a load. The controller can determine the load demands a second number, greater than the first number, of active phases to supply the power. The controller can generate pulse signals and combine the pulse signals with the first clock signals to generate second clock signals having a higher frequency than the first clock signals. The controller can generate the PWM signals using the second clock signals to operate the second number of active phases in the power converter to supply power to the load.