公开(公告)号：US08102909B2

公开(公告)日：2012-01-24

申请号：US12783783

申请日：2010-05-20

申请人： Stuart D. Sandberg ,  Arnon Friedmann ,  Jelena Jovin ,  Bindu Chandna

发明人： Stuart D. Sandberg ,  Arnon Friedmann ,  Jelena Jovin ,  Bindu Chandna

IPC分类号： H03H7/30

CPC分类号： H04L25/03038 ,  H04L25/03019 ,  H04L2025/03414 ,  H04L2025/03477 ,  H04L2025/03611 ,  H04L2025/03617 ,  H04L2025/03764 ,  H04L2025/0377

摘要： Using a known or later developed time domain equalizer coefficient training algorithm, a least square solution for the time domain equalizer coefficients is taken at a starting point and iteratively improved on. In particular, the improvement is directed towards maximizing number of bits per frame loaded over the time domain equalizer coefficient choice. This can be accomplished by maximizing capacity directly rather than setting a goal to shorten the channel and hoping that the capacity will be maximized as a result.

摘要翻译： 使用已知或稍后开发的时域均衡器系数训练算法，在起点进行时域均衡器系数的最小二乘解，迭代改进。 特别地，改进旨在通过时域均衡器系数选择来最大化每帧加载的比特数。 这可以通过直接最大化容量来实现，而不是设定缩短通道的目标，并希望能够最大化容量。

公开(公告)号：US08077762B2

公开(公告)日：2011-12-13

申请号：US12858005

申请日：2010-08-17

申请人： Oscar E. Agazzi

发明人： Oscar E. Agazzi

IPC分类号： H04B1/38

CPC分类号： H04L7/0062 ,  G01R31/3004 ,  G01R31/3008 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/318502 ,  G01R31/318552 ,  G01R31/318594 ,  H04B3/23 ,  H04B3/32 ,  H04L1/0054 ,  H04L1/006 ,  H04L1/242 ,  H04L7/0334 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03267 ,  H04L25/067 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/497 ,  H04L2025/03363 ,  H04L2025/03369 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03496 ,  H04L2025/03503 ,  H04L2025/03617 ,  H04L2025/03745

摘要： A method for controlling operation of a multi-pair gigabit transceiver. The multi-pair gigabit transceiver comprises a Physical Layer Control module (PHY Control), a Physical Coding Sublayer module (PCS) and a Digital Signal Processing module (DSP). The PHY Control receives user-defined inputs from the Serial Management module and status signals from the DSP and the PCS and generates control signals, responsive to the user-defined inputs, the status signals, to the DSP and the PCS.

摘要翻译： 一种用于控制多对千兆位收发器的操作的方法。 多对千兆位收发器包括物理层控制模块（PHY Control），物理编码子层模块（PCS）和数字信号处理模块（DSP）。 PHY控制从串行管理模块接收用户定义的输入和来自DSP和PCS的状态信号，并根据用户定义的输入，将状态信号产生到DSP和PCS的控制信号。

公开(公告)号：US20110293289A1

公开(公告)日：2011-12-01

申请号：US12791223

申请日：2010-06-01

申请人： David J. Krause ,  Han Henry Sun ,  John D. McNicol

发明人： David J. Krause ,  Han Henry Sun ,  John D. McNicol

IPC分类号： G06F17/10 ,  H04B10/00

CPC分类号： H04B10/616 ,  H04L25/0305 ,  H04L2025/03401 ,  H04L2025/03477 ,  H04L2025/03675

摘要： A system, method, and apparatus is disclosed for enabling a constant modulus algorithm (CMA) to be reliably used for blind equalization training of an equalizer. According to one embodiment, received signals in a binary phase shift keying (BPSK) format are converted to a quadrature phase shift keying (QPSK) format, to which CMA processing can be reliably applied for equalization. According to another aspect of this embodiment, the equalized QPSK signals are rotated to convert the signals to an equalized BPSK format for output.

摘要翻译： 公开了一种用于使恒模算法（CMA）可靠地用于均衡器的盲均衡训练的系统，方法和装置。 根据一个实施例，二进制相移键控（BPSK）格式的接收信号被转换成正交相移键控（QPSK）格式，CMA处理可以被可靠地应用于均衡。 根据本实施例的另一方面，均衡的QPSK信号被旋转以将信号转换成均衡的BPSK格式用于输出。

公开(公告)号：US20110293051A1

公开(公告)日：2011-12-01

申请号：US13110641

申请日：2011-05-18

申请人： Alexander N. LOZHKIN

发明人： Alexander N. LOZHKIN

IPC分类号： H03D1/04

CPC分类号： H04L25/03133 ,  H04L25/067 ,  H04L27/368 ,  H04L2025/03477 ,  H04L2025/03617

摘要： A receiving device which receives a signal transmitted from a transmitting device by using a power amplifier, the receiving device includes a calculating unit which performs distortion compensation on a symbol included in a reception signal, a delay unit which holds a signal for a result from the distortion compensation, and the calculating unit performing the distortion compensation on a second symbol at a timing later than a first symbol based on a coefficient corresponding to an amplification characteristic of the power amplifier and on the signal for the result from the distortion compensation with respect to the first symbol held by the delay unit.

摘要翻译： 一种接收装置，其通过使用功率放大器接收从发送装置发送的信号，所述接收装置包括对包含在接收信号中的符号进行失真补偿的计算单元，保持来自所述接收信号的结果的信号的延迟单元 失真补偿，以及所述计算单元，基于与所述功率放大器的放大特性相对应的系数，以及相对于所述功率放大器的失真补偿的结果的信号，在比所述第一符号稍晚的定时对第二符号执行失真补偿 由延迟单元持有的第一个符号。

公开(公告)号：US08031799B2

公开(公告)日：2011-10-04

申请号：US12849528

申请日：2010-08-03

申请人： Oscar E. Agazzi ,  John L. Creigh ,  Mehdi Hatamian ,  David E. Kruse ,  Arthur Abnous ,  Henry Samueli

发明人： Oscar E. Agazzi ,  John L. Creigh ,  Mehdi Hatamian ,  David E. Kruse ,  Arthur Abnous ,  Henry Samueli

IPC分类号： H04B15/00

CPC分类号： H04L7/0062 ,  G01R31/3004 ,  G01R31/3008 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/318502 ,  G01R31/318552 ,  G01R31/318594 ,  H04B3/23 ,  H04B3/235 ,  H04B3/32 ,  H04L1/0021 ,  H04L1/0047 ,  H04L1/0053 ,  H04L1/0054 ,  H04L1/0059 ,  H04L1/006 ,  H04L1/242 ,  H04L7/0334 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03197 ,  H04L25/03203 ,  H04L25/03235 ,  H04L25/03267 ,  H04L25/03987 ,  H04L25/067 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/497 ,  H04L2001/0096 ,  H04L2025/03363 ,  H04L2025/03369 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03496 ,  H04L2025/03503 ,  H04L2025/03617 ,  H04L2025/03745

摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

摘要翻译： 公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。 基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。 通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。 生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。 调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

公开(公告)号：US20110150071A1

公开(公告)日：2011-06-23

申请号：US12905912

申请日：2010-10-15

申请人： Hiroshi Takatori ,  Albert Vareljian ,  Alex (Oleksiy) Zabroda

发明人： Hiroshi Takatori ,  Albert Vareljian ,  Alex (Oleksiy) Zabroda

IPC分类号： H04L27/06 ,  H04L27/01

CPC分类号： H04L25/03038 ,  H03H11/26 ,  H03H11/46 ,  H03H15/02 ,  H03H21/0001 ,  H04B3/32 ,  H04L1/0047 ,  H04L25/03057 ,  H04L25/03133 ,  H04L25/03343 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03503 ,  H04L2025/03598

摘要： According to an embodiment of the disclosure, a communication transmitter and receiver include an adaptive filter and a decision feedback equalizer as well as cross-talk cancellers. The adaptive filter is configured to receive an input signal and includes a continuous analog delay circuit with a plurality of Padé-based delay elements.

摘要翻译： 根据本公开的实施例，通信发射机和接收机包括自适应滤波器和判决反馈均衡器以及串扰消除器。 自适应滤波器被配置为接收输入信号并且包括具有多个基于Padé的延迟元件的连续模拟延迟电路。

公开(公告)号：US07831648B2

公开(公告)日：2010-11-09

申请号：US11393107

申请日：2006-03-30

申请人： Gerald L. Fudge

发明人： Gerald L. Fudge

IPC分类号： G06F17/10

CPC分类号： H04L25/03038 ,  H04L2025/03477

摘要： The present invention is a method and computer program for equalizing group delay and magnitude of a system for which a system response is known. The method and computer program are implemented via a finite impulse response (“FIR”) filter for the system, and the method broadly comprises the steps of: evaluating a desired response for the system as a function of an amplitude of the system and a phase of the system; separating the phase of the system into a linear component and a non-linear component; performing a first optimization by minimizing a weighted error between a desired response for the system and a cascaded response for the system as a function of an equalizing filter and a phase slope so as to obtain at least one local smallest error E(Ω) as a function of phase slope; and once the local smallest error E(Ω) is known, performing a second optimization to locate any existing global smallest error, wherein the global smallest error is within a set distance from the local smallest error.

摘要翻译： 本发明是用于均衡系统响应已知的系统的组延迟和幅度的方法和计算机程序。 该方法和计算机程序通过用于系统的有限脉冲响应（“FIR”）滤波器来实现，并且该方法广泛地包括以下步骤：根据系统的幅度和相位来评估系统的期望响应 的系统; 将系统的相位分离成线性分量和非线性分量; 通过最小化系统的期望响应和作为均衡滤波器和相位斜率的函数的系统的级联响应之间的加权误差来执行第一优化，以便获得至少一个局部最小误差E（＆OHgr）作为 相位函数; 并且一旦已知本地最小误差E（＆OHgr;），则执行第二优化以定位任何现有的全局最小误差，其中全局最小误差在距离局部最小误差的设定距离内。

公开(公告)号：US07769101B2

公开(公告)日：2010-08-03

申请号：US11846195

申请日：2007-08-28

申请人： Oscar E. Agazzi ,  John L. Creigh ,  Mehdi Hatamian ,  David E. Kruse ,  Arthur Abnous ,  Henry Samueli

发明人： Oscar E. Agazzi ,  John L. Creigh ,  Mehdi Hatamian ,  David E. Kruse ,  Arthur Abnous ,  Henry Samueli

IPC分类号： H04B15/00

CPC分类号： H04L7/0062 ,  G01R31/3004 ,  G01R31/3008 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/318502 ,  G01R31/318552 ,  G01R31/318594 ,  H04B3/23 ,  H04B3/235 ,  H04B3/32 ,  H04L1/0021 ,  H04L1/0047 ,  H04L1/0053 ,  H04L1/0054 ,  H04L1/0059 ,  H04L1/006 ,  H04L1/242 ,  H04L7/0334 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03197 ,  H04L25/03203 ,  H04L25/03235 ,  H04L25/03267 ,  H04L25/03987 ,  H04L25/067 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/497 ,  H04L2001/0096 ,  H04L2025/03363 ,  H04L2025/03369 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03496 ,  H04L2025/03503 ,  H04L2025/03617 ,  H04L2025/03745

摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

摘要翻译： 公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。 基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。 通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。 生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。 调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

公开(公告)号：US20100189171A1

公开(公告)日：2010-07-29

申请号：US12751490

申请日：2010-03-31

申请人： Gottfried Ungerboeck

发明人： Gottfried Ungerboeck

IPC分类号： H04L27/01

CPC分类号： H04L25/03343 ,  H04L25/03038 ,  H04L25/49 ,  H04L27/3405 ,  H04L2025/03375 ,  H04L2025/03477

摘要： A method for modulating a sequence of data symbols such that the transmit signal exhibits spectral redundancy. Null symbols are inserted in the sequence of data symbols such that a specified pattern of K data symbols and N−K null symbols is formed in every period of N symbols in the modulated sequence, N and K being positive integers and K being smaller than N.

摘要翻译： 一种用于调制数据符号序列使得发送信号表现出频谱冗余的方法。 在数据符号序列中插入空符号，使得在调制序列中的N个符号的每个周期中形成K个数据符号和N-K个空符号的指定模式，N和K是正整数，K小于N 。

公开(公告)号：US07760797B2

公开(公告)日：2010-07-20

申请号：US11671522

申请日：2007-02-06

申请人： Dong-Wook Seo ,  Gi-Bong Jeong ,  Il-Yong Jong ,  Hee-Su Kim

发明人： Dong-Wook Seo ,  Gi-Bong Jeong ,  Il-Yong Jong ,  Hee-Su Kim

IPC分类号： H03K5/159

CPC分类号： H04L25/03038 ,  H04L2025/03407 ,  H04L2025/03477

摘要： A method of reducing a number of computations in an equalization process includes performing a pre-equalization operation on selected first frames from a plurality of frames, and estimating pre-equalization values of second frames based on the pre-equalization values of selected first frames, the second frames being frames which are not selected from the plurality of frames.

摘要翻译： 一种减少均衡处理中的计算次数的方法包括：从多个帧中对所选择的第一帧执行预均衡操作，以及基于所选择的第一帧的预均衡值来估计第二帧的预均衡值， 第二帧是不是从多个帧中选择的帧。