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    Programming Methods For Neural Network Using Non-volatile Memory Array
    291.
    发明申请
    Programming Methods For Neural Network Using Non-volatile Memory Array 审中-公开

    公开(公告)号：US20200151543A1

    公开(公告)日：2020-05-14

    申请号：US16746852

    申请日：2020-01-18

    Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

    Inventor： Farnood Merrikh BAYAT ,  Xinjie GUO ,  Dmitri STRUKOV ,  Nhan DO ,  Hieu Van TRAN ,  Vipin TIWARI ,  Mark REITEN

    IPC: G06N3/04 ,  G06F3/06 ,  G06N3/063

    Abstract: An artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses. The synapses are configured to receive inputs and to generate therefrom outputs. Neurons are configured to receive the outputs. The synapses include a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the inputs by the stored weight values to generate the outputs. Various algorithms for tuning the memory cells to contain the correct weight values are disclosed.

    Method Of Making Split Gate Non-volatile Flash Memory Cell
    295.
    发明申请
    Method Of Making Split Gate Non-volatile Flash Memory Cell 审中-公开

    公开(公告)号：US20200020789A1

    公开(公告)日：2020-01-16

    申请号：US16576370

    申请日：2019-09-19

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

    IPC: H01L29/66 ,  H01L27/11521 ,  H01L21/3213

    Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

    Address Fault Detection In A Flash Memory System
    296.
    发明申请
    Address Fault Detection In A Flash Memory System 审中-公开

    公开(公告)号：US20190378548A1

    公开(公告)日：2019-12-12

    申请号：US16551593

    申请日：2019-08-26

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Xian Liu ,  Nhan Do

    IPC: G11C7/10 ,  H01L21/28 ,  H01L27/11521 ,  G11C8/12

    Abstract: A system and method are disclosed for performing address fault detection in a flash memory system. In one embodiment, a flash memory system comprises a memory array comprising flash memory cells arranged in rows and columns, a row decoder for receiving a row address as an input, the row decoder coupled to a plurality of word lines, wherein each word line is coupled to a row of flash memory cells in the memory array, an address fault detection array comprising a column of memory cells, wherein each of the plurality of word lines is coupled to a memory cell in the column, and an analog comparator for comparing a current drawn by the column with a reference current and for indicating a fault if the current drawn by the column exceeds the reference current.

    Sacrificial alignment ring and self-soldering vias for wafer bonding
    299.
    发明授权
    Sacrificial alignment ring and self-soldering vias for wafer bonding 有权

    公开(公告)号：US10381330B2

    公开(公告)日：2019-08-13

    申请号：US15921563

    申请日：2018-03-14

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Justin Hiroki Sato ,  Bomy Chen ,  Walter Lundy

    IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

    Abstract: A method of bonding a first substrate to a second substrate, wherein the first substrate includes first electrical contacts on a top surface of the first substrate, and wherein the second substrate includes second electrical contacts on a bottom surface of the second substrate. The method includes forming a block of polyimide on the top surface of the first substrate, wherein the block of polyimide has a rounded upper corner, and vertically moving the top surface of the first substrate and the bottom surface of the second substrate toward each other until the first electrical contacts abut the second electrical contacts, wherein during the moving, the second substrate makes contact with the rounded upper corner of the polyimide causing the first and second substrates to move laterally relative to each other.

    Neural Network Classifier Using Array Of Four-Gate Non-volatile Memory Cells
    300.
    发明申请
    Neural Network Classifier Using Array Of Four-Gate Non-volatile Memory Cells 审中-公开

    公开(公告)号：US20190237142A1

    公开(公告)日：2019-08-01

    申请号：US16382034

    申请日：2019-04-11

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

    IPC: G11C16/04 ,  H01L27/11517 ,  G06N3/04

    Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region, and second and third gates over the floating gate and over the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the third gates in one of the memory cell rows, fourth lines each electrically connect the source regions in one of the memory cell rows, and fifth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first, second or third lines, and provide a first plurality of outputs as electrical currents on the fifth lines.

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