UNIVERSAL HOUSING FOR PLUGGABLE NETWORK INTERFACE DEVICES

    公开(公告)号:US20250096509A1

    公开(公告)日:2025-03-20

    申请号:US18370748

    申请日:2023-09-20

    Abstract: A pluggable network interface device includes a printed circuit board (“PCB”) and a housing configured to receive a heat transfer plate selected from a set of swappable heat transfer plates. An upper surface of the housing includes a set of modular plate receiving features. When in an assembled state, the upper surface of the housing is attached via the set of modular plate receiving features to one heat transfer plate of a set of heat transfer plates. The overall height of the pluggable network interface module in the assembled state is greater than a first assembly height dimension measured from a base surface of the housing to the upper surface of the housing. The set of modular plate receiving features are configured to engage with any heat transfer plate in the set of swappable heat transfer plates that are associated with different module types.

    Mirror image of geometrical patterns in stacked integrated circuit dies

    公开(公告)号:US12255178B2

    公开(公告)日:2025-03-18

    申请号:US17584450

    申请日:2022-01-26

    Inventor: Ido Bourstein

    Abstract: An electronic device includes a first integrated circuit (IC) die and a second IC die. The first IC die includes a first set of contact pads arranged in a first geometrical pattern on a first surface of the first IC die, the second IC die includes a second set of the contact pads that are arranged, on a second surface of the second IC die, in a second geometrical pattern that is a mirror image of the first geometrical pattern. The second surface of the second IC die is facing the first surface of the first IC die, and the contact pads of the first and second sets are aligned with one another and mounted on one another.

    DIRECT CONTACT HEAT TRANSFER COUPLINGS FOR PLUGGABLE NETWORK INTERFACE DEVICES

    公开(公告)号:US20250089152A1

    公开(公告)日:2025-03-13

    申请号:US18367094

    申请日:2023-09-12

    Abstract: A pluggable network interface device includes a printed circuit board (“PCB”), a housing, and a heatsink. The heatsink includes a first surface and a second surface, disposed opposite the first surface, that is maintained in direct contact with a surface of a heat-generating circuit of the PCB. The housing includes an outer shell defining an exterior of the housing, a receiving cavity disposed inside the outer shell, and an aperture extending through a first side of the outer shell from the exterior of the housing into the receiving cavity. A portion of the PCB and the second surface of the heatsink are disposed inside the receiving cavity while a portion of the heatsink extends from within the receiving cavity through the aperture arranging the first surface of the heatsink adjacent the exterior of the housing.

    FLEXIBLE HARDWARE COMPONENT DRIVER LOADING

    公开(公告)号:US20250077236A1

    公开(公告)日:2025-03-06

    申请号:US18242269

    申请日:2023-09-05

    Abstract: System, methods, and devices for initializing a system by loading drivers are provided. In one example, a system includes comprising one or more circuits to initiate a system initiation or a boot of the system, during the system initiation or the boot of the system, read data from a non-volatile memory, based on the data from the non-volatile memory, identify a plurality of hardware components, identify one or more drivers based on the plurality of hardware components, and load the one or more drivers during the system initiation or the boot of the system.

    GLOBAL BANDWIDTH-AWARE ADAPTIVE ROUTING

    公开(公告)号:US20250071063A1

    公开(公告)日:2025-02-27

    申请号:US18377642

    申请日:2023-10-06

    Abstract: Systems and methods herein are for global bandwidth-aware adaptive routing in a network communication and include at least one switch to determine an event associated with a change in network bandwidth between a local host and a remote host, where the at least one switch is further to provide routing protocols for the network communication, and where the routing protocols is to be used to modify an adaptive routing in the at least one switch for selection from different routes for the network communication between the local host and the remote host.

    Efficient network device work queue
    308.
    发明授权

    公开(公告)号:US12224950B2

    公开(公告)日:2025-02-11

    申请号:US17979018

    申请日:2022-11-02

    Abstract: In one embodiment, a system includes a memory to store a work queue including work queue entry slots, a processing device to write work queue entries to the work queue in a consecutive and cyclic manner, and a network device including a network interface to share packet over a network, and packet processing circuitry to read the work queue entries from the work queue in a consecutive and cyclic manner, the work queue entries indicating work to be performed associated with the packets, dequeue respective ones of the work queue entries read from the work queue responsively to reading the respective work queue entries from the work queue, add the work queue entries to an execution database used to track execution of the work queue entries, and execute the work queue entries in the execution database.

    POWER-OPTIMIZED AND SHARED BUFFER
    309.
    发明申请

    公开(公告)号:US20250044981A1

    公开(公告)日:2025-02-06

    申请号:US18229509

    申请日:2023-08-02

    Abstract: A network device, a network interface controller, and a switch are provided. In one example, a shared buffer includes a plurality of cells of memory, one or more ports read data from the shared buffer and write data to the shared buffer, and a controller circuit selectively enables and disables cells of memory of the shared buffer based on an amount of data stored in the shared buffer. Power consumption of the shared buffer is in proportion to a number of enabled cells of memory.

    Peripheral device with cache updating from multiple sources

    公开(公告)号:US12216580B1

    公开(公告)日:2025-02-04

    申请号:US18456536

    申请日:2023-08-28

    Abstract: A peripheral device includes a processor, a memory interface, a host interface and a cache controller. The processor executes software code. The cache memory caches a portion of the software code. The memory interface communicates with a NVM storing a replica of the software code. The host interface communicates with hosts storing additional replicas of the software code. The cache controller is to determine whether each host is allocated for code fetching, to receive a request from the processor for a segment of the software code, when available in the cache memory to fetch the segment from the cache memory, when unavailable in the cache memory and at least one host is allocated, to fetch the segment from the hosts that are allocated, when unavailable in the cache memory and no host is allocated, to fetch the segment from the NVM, and to serve the fetched segment to the processor.

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