公开(公告)号：US07541241B2

公开(公告)日：2009-06-02

申请号：US11298836

申请日：2005-12-12

Applicant: Jai Hoon Sim ,  Jih Wen Chou

Inventor： Jai Hoon Sim ,  Jih Wen Chou

IPC: H01L21/336

CPC classification number: H01L27/10894 ,  H01L27/10876 ,  H01L29/41783 ,  H01L29/66553 ,  H01L29/66621

Abstract: A memory cell structure comprises a semiconductor substrate, two stack structures positioned on the semiconductor substrate, two conductive spacers positioned on sidewalls of the two stack structures, a gate oxide layer covering a portion of the semiconductor substrate between the two conductive spacers and a gate structure positioned at least on the gate oxide layer. Particularly, each of two stack structures includes a first oxide block, a conductive block and a second oxide block, and the two conductive spacers are positioned at on the sidewall of the two conductive blocks of the two stack structures. The two conductive spacers are preferably made of polysilicon, and have a top end lower than the bottom surface of the second oxide block. In addition, a dielectric spacer is positioned on each of the two conductive spacers.

Abstract translation: 存储单元结构包括半导体衬底，位于半导体衬底上的两个堆叠结构，位于两个堆叠结构的侧壁上的两个导电间隔物，覆盖两个导电间隔物之间​​的半导体衬底的一部分的栅极氧化物层和栅极结构 至少位于栅极氧化物层上。 特别地，两个堆叠结构中的每一个包括第一氧化物块，导电块和第二氧化物块，并且两个导电间隔物位于两个堆叠结构的两个导电块的侧壁上。 两个导电间隔物优选由多晶硅制成，并且具有比第二氧化物块的底表面低的顶端。 此外，介电隔离物位于两个导电间隔物中的每一个上。

公开(公告)号：US07541116B2

公开(公告)日：2009-06-02

申请号：US11254729

申请日：2005-10-21

Applicant: Chun Yu Lin

Inventor： Chun Yu Lin

IPC: G03F1/00

CPC classification number: G03F1/28 ,  G03F1/50 ,  G03F7/70283

Abstract: A mask at frequency domain comprises a plurality of amplitude patterns positioned on a first surface of the mask and a plurality of phase patterns positioned on a second surface of the mask. The amplitude patterns have different vertical thicknesses to change the amplitude of an exposing light, and the phase patterns have different vertical thicknesses to change the phase of the exposing light. Preferably, the amplitude patterns are made of inorganic material, such as molybdenum silicide (MoSi), and the phase patterns are made of transparent material, such as quartz. The amplitude patterns and phase patterns are the Fourier transform of a circuit layout, and their numbers and positions are correspondent with each other.

Abstract translation: 在频域处的掩模包括位于掩模的第一表面上的多个幅度图案和位于掩模的第二表面上的多个相位图案。 幅度图案具有不同的垂直厚度以改变曝光光的幅度，并且相位图案具有不同的垂直厚度以改变曝光光的相位。 优选地，幅度图案由诸如硅化钼（MoSi）的无机材料制成，并且相图由诸如石英的透明材料制成。 幅度图案和相位图案是电路布局的傅里叶变换，它们的数量和位置彼此对应。

公开(公告)号：US07538043B2

公开(公告)日：2009-05-26

申请号：US11615909

申请日：2006-12-22

Applicant: Chien-Min Lee

Inventor： Chien-Min Lee

IPC: H01L21/31

CPC classification number: H01L45/1675 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: A phase change memory device comprising an electrode, a phase change layer crossing and contacting the electrode at a cross region thereof, and a transistor comprising a source and a drain, wherein the drain of the transistor electrically connects the electrode or the phase change layer is disclosed.

Abstract translation: 一种相变存储器件，包括电极，在其交叉区域交叉并接触电极的相变层和包括源极和漏极的晶体管，其中晶体管的漏极电连接电极或相变层是 披露

公开(公告)号：US07538018B2

公开(公告)日：2009-05-26

申请号：US11670427

申请日：2007-02-02

Applicant: Jung-Wu Chien

Inventor： Jung-Wu Chien

IPC: H01L21/28

CPC classification number: H01L29/66621 ,  H01L21/28061 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/66583

Abstract: A method for fabricating a gate structure is provided. A pad oxide layer, a pad conductive layer and a dielectric layer are sequentially formed over a substrate. A portion of the dielectric layer is removed to form an opening exposing a portion of the pad conductive layer. A liner conductive layer is formed to cover the dielectric layer and the pad conductive layer. A portion of the liner conductive layer and a portion of the pad conductive layer are removed to expose a surface of the pad oxide layer to form a conductive spacer. The pad oxide layer is removed and a gate oxide layer is formed over the substrate. A first gate conductive layer and a second gate conductive layer are sequentially formed over the gate oxide layer. A portion of the gate oxide layer is removed and a cap layer to fill the opening.

Abstract translation: 提供一种制造栅极结构的方法。 衬底氧化物层，焊盘导电层和电介质层依次形成在衬底上。 去除介电层的一部分以形成露出焊盘导电层的一部分的开口。 形成衬垫导电层以覆盖电介质层和焊盘导电层。 去除衬垫导电层的一部分和焊盘导电层的一部分以暴露衬垫氧化物层的表面以形成导电间隔物。 去除衬垫氧化物层，并在衬底上形成栅氧化层。 在栅极氧化物层上顺序地形成第一栅极导电层和第二栅极导电层。 去除栅极氧化物层的一部分，并且覆盖层以填充开口。

公开(公告)号：US07535050B2

公开(公告)日：2009-05-19

申请号：US11272683

申请日：2005-11-15

Applicant: Chih-Ping Chung ,  Chun-Nan Lin ,  Chung-Yi Chen ,  Hung-Kwei Liao

Inventor： Chih-Ping Chung ,  Chun-Nan Lin ,  Chung-Yi Chen ,  Hung-Kwei Liao

IPC: H01L29/94

CPC classification number: H01L29/42324 ,  H01L21/28273

Abstract: A memory structure comprising a plurality of memory cells is described. Each memory cell comprises a substrate, a shallow trench isolation, a spacer, a tunnel oxide, and a floating gate. The shallow trench isolation in the substrate is used to define an active area. The spacer is at the sidewall of the shallow trench isolation and is higher than the shallow trench isolation. The tunnel oxide is on the active area. The floating gate is on the tunnel oxide.

Abstract translation: 描述包括多个存储器单元的存储器结构。 每个存储单元包括衬底，浅沟槽隔离，间隔物，隧道氧化物和浮动栅极。 衬底中的浅沟槽隔离用于限定有源区。 间隔物位于浅沟槽隔离物的侧壁处，并且高于浅沟槽隔离。 隧道氧化物在有源区上。 浮动栅极在隧道氧化物上。

公开(公告)号：US20090117699A1

公开(公告)日：2009-05-07

申请号：US12033400

申请日：2008-02-19

Applicant: HUNG YANG LIN

Inventor： HUNG YANG LIN

IPC: H01L21/336

CPC classification number: H01L29/1037 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/66583 ,  H01L29/66621 ,  H01L29/78

Abstract: A method for preparing a recessed transistor structure comprises the steps of performing an implanting process to form a doped layer in a substrate, forming a plurality of gate-isolation blocks on the substrate, forming a plurality of first spacers on sidewalls of the gate-isolation blocks, removing a portion of the substrate not covered by the first spacers and the gate-isolation blocks to form a plurality of depressions in the substrate between the first spacers, forming a gate oxide layer on inner sidewalls of the depressions, and forming a gate structure on the gate oxide layer to complete the recessed transistor structure.

Abstract translation: 一种用于制备凹陷晶体管结构的方法包括以下步骤：执行注入工艺以在衬底中形成掺杂层，在衬底上形成多个栅极隔离块，在栅极隔离的侧壁上形成多个第一间隔物 除去未被第一间隔物和栅极隔离块覆盖的衬底的一部分，以在第一间隔物之间​​的衬底中形成多个凹陷，在凹陷的内侧壁上形成栅极氧化层，并形成栅极 结构在栅极氧化层上完成凹陷的晶体管结构。

公开(公告)号：US20090101880A1

公开(公告)日：2009-04-23

申请号：US11964618

申请日：2007-12-26

Applicant: Li-Shu Tu

Inventor： Li-Shu Tu

IPC: H01L47/00 ,  B05D5/12

CPC classification number: H01L45/06 ,  H01L27/2463 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: An exemplary memory device includes a first dielectric layer with a first conductive contact therein. A phase change material (PCM) is disposed on top of the first dielectric layer and provided with an insulating layer integrally on a top surface of the PCM. A first electrode is disposed over the first dielectric layer and covered a portion of the first conductive contact and the insulating layer in a first direction, contacting to the first conductive contact and a first side of the PCM. A second electrode is disposed over the first dielectric layer and covered a portion of the insulating layer in a second direction, contacting to a second side of the PCM. A second dielectric layer is disposed over the first dielectric layer to cover the first electrode, the second electrode, the insulating layer and the PCM, including a second conductive contact connected to the second electrode.

Abstract translation: 示例性的存储器件包括其中具有第一导电触点的第一介电层。 相变材料（PCM）设置在第一电介质层的顶部并且在PCM的顶表面上一体地设置有绝缘层。 第一电极设置在第一电介质层之上并且在第一方向上覆盖第一导电接触部分和绝缘层的一部分，与第一导电接触件和PCM的第一侧接触。 第二电极设置在第一电介质层之上并且在第二方向上覆盖绝缘层的一部分，接触PCM的第二侧。 第二电介质层设置在第一电介质层上以覆盖第一电极，第二电极，绝缘层和PCM，包括连接到第二电极的第二导电触点。

公开(公告)号：US07521372B2

公开(公告)日：2009-04-21

申请号：US11617977

申请日：2006-12-29

Applicant: Frederick T Chen

Inventor： Frederick T Chen

IPC: H01L45/00

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

Abstract: A phase-change memory and fabrication method thereof. The phase-change memory comprises a transistor, and a phase-change material layer. In particular, the phase-change material layer is directly in contact with one electrical terminal of the transistor. Particularly, the transistor can be a field effect transistor or a bipolar junction transistor.

Abstract translation: 一种相变存储器及其制造方法。 相变存储器包括晶体管和相变材料层。 特别地，相变材料层与晶体管的一个电端子直接接触。 特别地，晶体管可以是场效应晶体管或双极结型晶体管。

公开(公告)号：US20090078926A1

公开(公告)日：2009-03-26

申请号：US12328745

申请日：2008-12-04

Applicant: Chien-Min Lee

Inventor： Chien-Min Lee

IPC: H01L45/00

CPC classification number: H01L45/1675 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: A phase change memory device comprising an electrode, a phase change layer crossing and contacting the electrode at a cross region thereof, and a transistor comprising a source and a drain, wherein the drain of the transistor electrically connects the electrode or the phase change layer is disclosed.

Abstract translation: 一种相变存储器件，包括电极，在其交叉区域交叉并接触电极的相变层和包括源极和漏极的晶体管，其中晶体管的漏极电连接电极或相变层是 披露

公开(公告)号：US20090062954A1

公开(公告)日：2009-03-05

申请号：US12115555

申请日：2008-05-06

Applicant: Yung-Yao Lee ,  Cheng-Fa Lin

Inventor： Yung-Yao Lee ,  Cheng-Fa Lin

IPC: G06F17/00

CPC classification number: G05B19/418 ,  G05B2219/32266 ,  G05B2219/32267 ,  Y02P90/02 ,  Y02P90/20 ,  Y02P90/22

Abstract: A method and a system for auto-dispatching lots in a photolithography process are provided. According to the method, first, a prioritized lot list is established according to the working status of a plurality of photolithography equipments. Then, a processable lot with the highest priority from the lot list is selected and a relative process background information is used for determining a photolithography operation type. Finally, the selected lot is dispatched according to the photolithography operation type. The present invention dispatches the lot with the appropriate dispatching rule according to the process background information of the lot. As a result, the quality of the photolithography process can be ensured so as to increase the throughput, and the labor overhead can be reduced to achieve the purpose of production cost reduction.

Abstract translation: 提供了一种用于在光刻工艺中自动调度批次的方法和系统。 根据该方法，首先，根据多个光刻设备的工作状态建立优先的批次列表。 然后，选择具有来自批次列表的最高优先级的可处理批次，并且使用相对过程背景信息来确定光刻操作类型。 最后，根据光刻操作类型调度所选批次。 本发明根据批次的处理背景信息，用适当的调度规则调度批次。 结果，可以确保光刻工艺的质量，从而提高生产量，并且可以减少劳动开销以实现生产成本降低的目的。