公开(公告)号：US10236480B2

公开(公告)日：2019-03-19

申请号：US16031099

申请日：2018-07-10

Applicant: STMicroelectronics (Tours) SAS

Inventor： Ludovic Fallourd

IPC: H01M2/04 ,  H01M2/06 ,  H01M2/20 ,  H01M10/04 ,  H01M2/30 ,  H01M2/10

Abstract: Disclosed herein is an electronic device including a substrate, with an active layer stack on the substrate. A cover is on the active layer stack and has a surface area greater than that of the active layer so as to encapsulate the active layer stack. A conductive pad layer is on the cover. At least one conductive via extends between the active layer stack and the conductive pad layer.

公开(公告)号：US10211326B2

公开(公告)日：2019-02-19

申请号：US15362919

申请日：2016-11-29

Applicant: STMicroelectronics (Tours) SAS

Inventor： Samuel Menard

IPC: H01L29/747 ,  H01L29/66 ,  H01L29/40

Abstract: A vertical power component includes a doped silicon substrate of a first conductivity type. A local well of a second conductivity type extends from an upper surface of the substrate. A passivation structure coats a peripheral region of the upper surface side of the substrate surrounding the well. This passivation structure includes, on top of and in contact with the peripheral substrate region, a first region made of a first passivation material and a second region made of a second passivation material. The second region generates, in a surface region of the substrate in contact with said second region, a local increase of the concentration of majority carriers in the substrate.

公开(公告)号：US20190043972A1

公开(公告)日：2019-02-07

申请号：US16052378

申请日：2018-08-01

Applicant: STMicroelectronics (Tours) SAS

Inventor： Samuel MENARD

IPC: H01L29/747 ,  H01L29/66

CPC classification number: H01L29/747 ,  H01L29/0619 ,  H01L29/0839 ,  H01L29/42308 ,  H01L29/66386 ,  H01L29/7404

Abstract: A one-way switch has a gate referenced to a main back side electrode. An N-type substrate includes a P-type anode layer covering a back side and a surrounding P-type wall. First and second P-type wells are formed on the front side of the N-type substrate. An N-type cathode region is located in the first P-type well. An N-type gate region is located in the second P-type well. A gate metallization covers both the N-type gate region and a portion of the second P-type well. The second P-type well is separated from the P-type wall by the N-type substrate except at a location of a P-type strip that is formed in the N-type substrate and connects a portion on one side of the second P-type well to an upper portion of said P-type wall.

公开(公告)号：US20190006960A1

公开(公告)日：2019-01-03

申请号：US16020413

申请日：2018-06-27

Applicant: STMicroelectronics (Tours) SAS

Inventor： Ghafour BENABDELAZIZ ,  Cedric REYMOND ,  David JOUVE

IPC: H02M7/797 ,  H02M1/08

Abstract: A reversible converter includes a first field effect transistor and a second field effect transistor that are coupled in series between a first terminal and a second terminal for a DC voltage. A first triac and a second triac are also coupled in series between the first and second terminals of the DC voltage. Midpoints of the series coupled devices are coupled, through an inductive element, to first and second terminals for an AC voltage. Actuation of the transistors and triacs is controlled in distinct manners to operate the converter in an AC-DC conversion mode and a DC-AC conversion mode.

公开(公告)号：US20180331577A1

公开(公告)日：2018-11-15

申请号：US15925356

申请日：2018-03-19

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Jean Pierre Proot ,  Pascal Paillet

IPC: H02J50/12 ,  H04B5/00 ,  H02J50/80

Abstract: A resonant circuit can be used in recharging a battery. The resonant circuit includes an inductor, a first capacitor in series with the inductor, and a second capacitor in parallel with the inductor. Upon entering the field of a charging terminal a controller connected to the resonant circuit continually measures loss in the inductor and voltage on a terminal of the resonant circuit. If both are below respective predetermined thresholds, the controller decreases the capacitance of the first capacitor and increases the capacitance of the second capacitor, thereby increasing voltage from the resonant circuit to the battery.

公开(公告)号：US10103705B2

公开(公告)日：2018-10-16

申请号：US14632981

申请日：2015-02-26

Applicant: STMicroelectronics (Tours) SAS

Inventor： Sylvain Charley ,  Aline Noire

IPC: H02M3/06 ,  H03H7/38 ,  H01G7/06 ,  H03H5/12 ,  H01G4/38

Abstract: A capacitor having a capacitance settable by biasing, including: a series association of a plurality of first capacitive elements between two first terminals defining the capacitor electrodes; and two second terminals of application of bias voltages respectively connected, via resistive elements, to the opposite electrodes of each of the first capacitive elements.

公开(公告)号：US10069170B2

公开(公告)日：2018-09-04

申请号：US15049766

申请日：2016-02-22

Applicant: STMicroelectronics (Tours) SAS

Inventor： Julien Ladroue ,  Mohamed Boufnichel

IPC: H01M10/0585 ,  H01M4/04 ,  H01M10/04 ,  H01M6/40

Abstract: A self-supporting thin-film battery is manufacture by forming on the upper surface of a support substrate a vertical active stack having as a lower layer a metal layer having formed therein a first contact terminal of a first polarity of the battery and having formed therein as an upper layer a metal layer having a second contact terminal of a second polarity of the battery. A support film is then bonded to an upper surface of the upper layer. The lower layer is the separated from the substrate by projecting a laser beam through the substrate from a lower surface thereof to impinge on the lower layer.

公开(公告)号：US10045420B2

公开(公告)日：2018-08-07

申请号：US14838519

申请日：2015-08-28

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Bertrand Rivet ,  David Jouve

IPC: H05B37/02 ,  H05B33/08 ,  G05F1/577 ,  H03K17/12 ,  H03K17/74 ,  H03K17/14

Abstract: A circuit is for balancing currents flowing through a parallel assembly of semiconductor components of the same type. The circuit may include a respective regulation circuit for each semiconductor component. Each regulation circuit may include a comparator of a first signal representative of the current flowing through the component with a reference signal, and a resistive element of a changeable resistance and controlled by the comparator.

公开(公告)号：US20180219194A1

公开(公告)日：2018-08-02

申请号：US15699233

申请日：2017-09-08

Applicant: STMicroelectronics (Tours) SAS

Inventor： Julien Ladroue ,  Mohamed Boufnichel

IPC: H01M2/06 ,  H01M10/0525 ,  H01M10/04 ,  H01M10/058 ,  H01M2/02

Abstract: A battery structure has structure anode and cathode contacts on a front face and on a rear face. The battery structure includes a battery having battery anode and cathode contacts only on a front face thereof. A film including a conductive layer and an insulating layer jackets the battery. The conductive layer extends over the battery anode and cathode contacts and is interrupted therebetween. Openings are provided in the insulating layer on the front and rear faces of the battery structure to form the structure anode and cathode contacts of the battery structure.

公开(公告)号：US09997623B2

公开(公告)日：2018-06-12

申请号：US14957803

申请日：2015-12-03

Applicant: STMicroelectronics (Tours) SAS

Inventor： Yannick Hague

IPC: H01L29/66 ,  H01L29/747 ,  H01L29/732 ,  H01L25/07 ,  H01L25/065 ,  H01L27/02 ,  H01L27/082

CPC classification number: H01L29/747 ,  H01L25/0652 ,  H01L25/072 ,  H01L27/0296 ,  H01L27/082 ,  H01L27/0823 ,  H01L29/1004 ,  H01L29/732 ,  H01L2224/06181 ,  H01L2224/48137

Abstract: A switch includes three components. Each component includes a stack of three semiconductor regions of alternating conductivity types and a control region in a first of the three semiconductor regions having a type opposite to that of the first semiconductor region. The first semiconductor regions of the first and second components are of a same conductivity type and the first semiconductor regions of the first and third components are of opposite conductivity types. The first semiconductor region of the first component is connected to the control regions of the second and third components. The first semiconductor regions of the second and third components are connected to a first switch terminal, the third semiconductor regions of the first, second, and third components are connected to a second switch terminal, and the control region of the first component is connected to a third switch terminal.