公开(公告)号：US11482530B2

公开(公告)日：2022-10-25

申请号：US16919697

申请日：2020-07-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: H01L27/11531 ,  G06N3/08 ,  G11C16/04 ,  H01L29/788

Abstract: Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

公开(公告)号：US20220319619A1

公开(公告)日：2022-10-06

申请号：US17839294

申请日：2022-06-13

Applicant: Silicon Storage Technology, Inc,

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Steven Lemke ,  Nha Nguyen ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/34 ,  G11C16/10 ,  G06N3/063 ,  G06F3/06 ,  G06N3/08 ,  G11C16/26 ,  G11C29/10

Abstract: Circuitry and methods are disclosed for compensating for leakage in analog neural memory in deep learning artificial neural networks. In one example, a method is disclosed of compensating for leakage in an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bitline, the method comprising measuring leakage for a column of analog neural non-volatile memory cells coupled to a bitline; storing the measured leakage value; and applying the measured leakage value during a read operation of the column of analog neural non-volatile memory cells to compensate for the leakage.

公开(公告)号：US11449741B2

公开(公告)日：2022-09-20

申请号：US16569647

申请日：2019-09-12

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Steven Lemke ,  Nha Nguyen ,  Vipin Tiwari ,  Nhan Do

IPC: G06N3/063 ,  G06N3/04 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/08

Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. The analog neural memory comprises one or more arrays of non-volatile memory cells. The testing circuitry and methods can be utilized during sort tests, qualification tests, and other tests to verify programming operations of one or more cells.

公开(公告)号：US11409352B2

公开(公告)日：2022-08-09

申请号：US16354040

申请日：2019-03-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten ,  Nhan Do

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3234 ,  G11C16/04 ,  G06N3/08 ,  G06F17/16 ,  G11C11/54 ,  G06N3/04

Abstract: Numerous embodiments of power management techniques are disclosed for various operations involving one or more vector-by-matrix multiplication (VMM) arrays within an artificial neural network.

公开(公告)号：US11362100B2

公开(公告)日：2022-06-14

申请号：US17069563

申请日：2020-10-13

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Steven Lemke ,  Hieu Van Tran ,  Nhan Do

IPC: H01L27/11517 ,  H01L27/11529 ,  H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11551

Abstract: Memory cells formed on upwardly extending fins of a semiconductor substrate, each including source and drain regions with a channel region therebetween, a floating gate extending along the channel region and wrapping around the fin, a word line gate extending along the channel region and wrapping around the fin, a control gate over the floating gate, and an erase gate over the source region. The control gates are a continuous conductive strip of material. First and second fins are spaced apart by a first distance. Third and fourth fins are spaced apart by a second distance. The second and third fins are spaced apart by a third distance greater than the first and second distances. The continuous strip includes a portion disposed between the second and third fins, but no portion of the continuous strip is disposed between the first and second fins nor between the third and fourth fins.

公开(公告)号：US11354562B2

公开(公告)日：2022-06-07

申请号：US15936983

申请日：2018-03-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stanley Hong ,  Anh Ly ,  Thuan Vu ,  Hien Pham ,  Kha Nguyen ,  Han Tran

IPC: G06N3/04 ,  G06F17/16 ,  G06N3/063 ,  G06N3/08 ,  G11C16/04 ,  G11C11/54 ,  H03F3/45

Abstract: Numerous embodiments for processing the current output of a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The embodiments comprise a summer circuit and an activation function circuit. The summer circuit and/or the activation function circuit comprise circuit elements that can be adjusted in response to the total possible current received from the VMM to optimize power consumption.

公开(公告)号：US11158374B2

公开(公告)日：2021-10-26

申请号：US16930777

申请日：2020-07-16

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Nhan Do ,  Vipin Tiwari ,  Mark Reiten

IPC: G11C16/04 ,  G06F17/16 ,  G06N3/063 ,  G06N3/08 ,  G06N3/04

Abstract: Numerous embodiments are disclosed for providing temperature compensation in a an analog memory array. The analog memory array optionally is a vector-by-matrix multiplier in an analog neuromorphic memory system used in a deep learning neural network. One embodiment comprises measuring an operating temperature within a memory array and applying, by a temperature compensation block, a bias voltage to a terminal of a memory cell in the array, wherein the bias voltage is a function of the operating temperature.

公开(公告)号：US20210280239A1

公开(公告)日：2021-09-09

申请号：US16986812

申请日：2020-08-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan VU ,  Stephen TRINH ,  Stanley HONG ,  Anh LY ,  Vipin Tiwari

IPC: G11C11/54 ,  G11C16/04 ,  G11C16/26 ,  G06N3/063

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are being read. In certain embodiments, weight mapping is performed adaptively for optimal performance in power and noise.

公开(公告)号：US20210210144A9

公开(公告)日：2021-07-08

申请号：US16574059

申请日：2019-09-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/12 ,  G11C16/04 ,  G11C16/24

Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed. In one embodiment, a programming circuit comprises a switch configured to couple a current source to a capacitor during a first mode and to uncouple the current source from the capacitor during the second mode, wherein during the second mode the capacitor is coupled to the gate of a transistor used to program a memory cell.

公开(公告)号：US20210209457A1

公开(公告)日：2021-07-08

申请号：US16830733

申请日：2020-03-26

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  STEVEN LEMKE ,  VIPIN TIWARI ,  NHAN DO ,  MARK REITEN

IPC: G06N3/063 ,  G06F11/16 ,  G11C29/44 ,  G11C13/00

Abstract: Numerous embodiments are provided for compensating for drift error in non-volatile memory cells within a VMM array in an analog neuromorphic memory system. For example, in one embodiment, a circuit is provided for compensating for drift error during a read operation, the circuit comprising a data drift monitoring circuit coupled to the array for generating an output indicative of data drift; and a bitline compensation circuit for generating a compensation current in response to the output from the data drift monitoring circuit and injecting the compensation current into one or more bitlines of the array.