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321.发明申请公开(公告)号：US20200020815A1
公开(公告)日：2020-01-16
申请号：US16581978
申请日：2019-09-25
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Karine SAXOD , Alexandre MAS , Eric SAUGIER , Gaetan LOBASCIO , Benoit BESANCON
IPC: H01L31/0203 , B29C45/14 , H01L31/12 , H01L31/02 , H01L31/0232 , H01L31/18
Abstract: A cover for an electronic package is manufactured by placing an optical insert, having opposite faces and configured to allow light radiation to pass therethrough, between two opposite faces of a cavity of a mold in a position such that said optical faces of the optical insert make contact with said opposite faces of the cavity of the mold. A coating material is injected into the cavity and around the optical insert. The coating material is set to obtain a substrate that is overmolded around the optical insert so as to produce the cover. An electronic package includes an electronic chip mounted to a support substrate with the cover formed by the overmolded substrate mounted to the support substrate.
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公开(公告)号：US20200006915A1
公开(公告)日：2020-01-02
申请号：US16569956
申请日：2019-09-13
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Research & Development) Limited
Inventor： Nicolas MOENECLAEY , Shatabda SAHA
Abstract: Disclosed herein is a method of optical pulse emission including three phases. During a first phase, a capacitor is charged from a supply voltage node. During a second phase, a voltage stored on the capacitor is boosted, and then the capacitor is at least partially discharged through a light emitting device. During a third phase, the capacitor is further discharged by bypassing the light emitting device. The third phase may begin prior to an end of the second phase.
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公开(公告)号：US10522899B2
公开(公告)日：2019-12-31
申请号：US16017611
申请日：2018-06-25
Inventor： David Auchere , Laurent Marechal , Yvon Imbs , Laurent Schwarz
IPC: H01Q1/22 , H01L23/31 , H01L21/56 , H01L23/66 , H01L21/3105 , H01L21/48 , H01L23/498
Abstract: An electronic device includes a support plate having a mounting face and an electrical connection network. An integrated circuit chip is mounted on the mounting face and linked to the electrical connection network. An encapsulation block embeds the integrated circuit chip. An additional element made of an electrically conductive material is at least partly embedded within the encapsulation block. The additional conductive element has a main portion extending parallel to the support plate and has a secondary portion that is linked electrically to the integrated circuit chip. An opening is formed in the encapsulation block, and the secondary portion extends into that opening to make the electrical link. The additional conductive element may be an antenna.
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公开(公告)号：US10520554B2
公开(公告)日：2019-12-31
申请号：US16269331
申请日：2019-02-06
Inventor： Vratislav Michal , Michel Ayraud
Abstract: A circuit includes an amplifier having a first power terminal configured to be coupled to a supply voltage and a second power terminal configured to be coupled to a reference potential. The circuit further includes a first impedance element coupled between a first input terminal of the amplifier and a first output terminal of the amplifier. The circuit additionally includes a second impedance element coupled between the first input terminal and the reference potential. The amplifier is configured to output a first voltage at a second output terminal of the amplifier in response to the supply voltage being greater than an output voltage at the first output terminal of the amplifier. The amplifier is further configured to output a second voltage at the second output terminal of the amplifier in response to the supply voltage being less than the output voltage at the first output terminal of the amplifier.
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公开(公告)号：US10480994B2
公开(公告)日：2019-11-19
申请号：US15611266
申请日：2017-06-01
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Karine Saxod , Jean-Michel Riviere
IPC: G01J1/02 , H01L25/16 , G01J1/04 , G01V8/10 , H05K1/18 , H05K3/28 , H01L31/0203 , H01L31/167
Abstract: A microchip has a rear face attached to a front mounting face of a support plate. An encapsulation cover for the microchip is mounted to the support plate. The encapsulation cover includes a front wall, a peripheral wall extending from the front wall and an inside partition extending from the front wall and between opposite sides of the peripheral wall. The inside partition passes locally above the microchip to delimit two cavities. A bonding material is interposed between encapsulation cover and the support plate and microchip. An end part of the inside partition of the cover, adjacent to the front face of the microchip, include an accumulation and containment recess that is configured to at least partly receive the bonding material.
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Patent Agency Ranking
公开(公告)号：US10455213B2
公开(公告)日：2019-10-22
申请号：US15467421
申请日：2017-03-23
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Jerome Chossat , Olivier Le-Briz
IPC: H04N13/207 , H04N13/254 , H01L27/146 , H04N5/369 , H04N13/271
Abstract: A three dimensional (3D) device is formed from a first level and a second level that are attached together. The first level includes a backside illuminated two dimensional (2D) image sensor including an array of first pixels sensitive to visible light. The second level includes a frontside illuminated depth sensor including an array of second pixels sensitive to near infrared light. The first and second levels are attached in a manner such that radiation, in particular the near infrared light, received at the backside of the first level passes through the first level to reach the depth sensor in the second level.
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公开(公告)号：US10454246B2
公开(公告)日：2019-10-22
申请号：US15052458
申请日：2016-02-24
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Research & Development) Limited
Inventor： Nicolas Moeneclaey , Shatabda Saha
Abstract: An optical pulse emitter includes a light emitting device having a first node coupled to an intermediate node via a first switch. The intermediate node is coupled to a supply voltage node via a second switch. A capacitor is coupled to the intermediate node. The first, second and third switches are controlled by a control circuit. During a first phase, the second switch is actuated to couple the capacitor to the supply voltage node. During a second phase, the second switch is deactuated and the first switch is actuated to at least partially discharge the capacitor through the light emitting device. During a third phase, discharge current from the capacitor bypasses around the light emitting device.
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公开(公告)号：US20190267922A1
公开(公告)日：2019-08-29
申请号：US16281604
申请日：2019-02-21
Inventor： Gwenael MAILLET , Jean-Louis LABYRE , Gilles BAS
IPC: H02P7/29 , G06K19/07 , G05B19/042
Abstract: Control over the operation of an electrically-controlled motor is supported by an interface circuit between the electrically-controlled motor and a near-field radio frequency communication controller. The interface circuit includes a first circuit that receives at least one control set point through a near-field radio frequency communication issued by the near-field radio frequency communication controller. A second circuit of the interface generates one or more electric signals in pulse width modulation based on the control set point.
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公开(公告)号：US10359800B2
公开(公告)日：2019-07-23
申请号：US15693214
申请日：2017-08-31
Inventor： Serge Ramet , Sandrine Nicolas , Danika Perrin , Cedric Rechatin
Abstract: An integrated circuit includes a first stage configured to receive a bias current. A current regulation loop includes a transimpedance amplifier having a first transistor, and a second transistor having a gate coupled to a gate of the first transistor. The first transistor and the second transistor are configured to compare the bias current with a reference current, and to generate a regulation voltage on an output node of the transimpedance amplifier. A capacitor is coupled between the output node of the transimpedance amplifier and the gates of the first and second transistors.
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公开(公告)号：US20190190606A1
公开(公告)日：2019-06-20
申请号：US16218948
申请日：2018-12-13
Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
Inventor： Jean-Michel RIVIERE , Romain COFFY , Karine SAXOD
CPC classification number: H04B10/40 , H01L31/0203 , H01L31/162 , H04B10/80 , H05K5/03 , H05K7/02
Abstract: A cover for an electronic circuit package, including: a body having an opening extending therethrough; a first element located in the opening and having a surface continuing planar or rounded shapes of a surface of the cover; and a second element of connection of the first element to the body.
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