公开(公告)号：US10796472B2

公开(公告)日：2020-10-06

申请号：US16024821

申请日：2018-06-30

Applicant: Intel Corporation

Inventor： Michael Apodaca ,  Ankur Shah ,  Ben Ashbaugh ,  Brandon Fliflet ,  Hema Nalluri ,  Pattabhiraman K ,  Peter Doyle ,  Joseph Koston ,  James Valerio ,  Murali Ramadoss ,  Altug Koker ,  Aditya Navale ,  Prasoonkumar Surti ,  Balaji Vembu

IPC: G06T15/00

Abstract: Apparatus and method for simultaneous command streamers. For example, one embodiment of an apparatus comprises: a plurality of work element queues to store work elements for a plurality of thread contexts, each work element associated with a context descriptor identifying a context storage region in memory; a plurality of command streamers, each command streamer associated with one of the plurality of work element queues, the command streamers to independently submit instructions for execution as specified by the work elements; a thread dispatcher to evaluate the thread contexts including priority values, to tag each instruction with an execution identifier (ID), and to responsively dispatch each instruction including the execution ID in accordance with the thread context; and a plurality of graphics functional units to independently execute each instruction dispatched by the thread dispatcher and to associate each instruction with a thread context based on its execution ID.

公开(公告)号：US10796401B2

公开(公告)日：2020-10-06

申请号：US16414251

申请日：2019-05-16

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Altug Koker ,  Abhishek R. Appu ,  Balaji Vembu

IPC: G06T1/60 ,  G06T1/20

Abstract: A mechanism is described for facilitating dynamic merging of atomic operations in computing devices. A method of embodiments, as described herein, includes facilitating detecting atomic messages and a plurality of slot addresses. The method further includes comparing one or more slot addresses of the plurality of slot addresses with other slot addresses of the plurality of slot addresses to seek one or more matched slot addresses, where the one or more matched slot addresses are merged into one or more merged groups. The method may further include generating one or more merged atomic operations based on and corresponding to the one or more merged groups.

公开(公告)号：US10776156B2

公开(公告)日：2020-09-15

申请号：US15281260

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Altug Koker ,  Prasoonkumar Surti ,  Guei-Yuan Lueh ,  Subramaniam Maiyuran ,  Tomas G. Akenine-Moller ,  David J. Cowperthwaite ,  Balaji Vembu

IPC: G06F9/46 ,  G06F9/48

Abstract: A processing apparatus is described. The apparatus includes a graphics processing unit (GPU), including a thread dispatcher to assign a priority class to each of a plurality of processing threads prior to dispatching the one or more processing threads, a plurality of execution units to process the threads, a shared resource coupled to each of the plurality of execution units and an arbitration unit to grant access to the shared resource to a first of the plurality of execution units based on the priority class of a thread being executed at the first execution unit.

公开(公告)号：US20200285480A1

公开(公告)日：2020-09-10

申请号：US16825129

申请日：2020-03-20

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker

IPC: G06F9/38 ,  G06F9/46 ,  G06T1/20 ,  G06F9/52 ,  G06F9/48 ,  G06F9/54 ,  G06F15/16 ,  G06F9/50 ,  G06F15/76 ,  G06F12/0897 ,  G06F12/0866 ,  G06T1/60

Abstract: An apparatus to facilitate thread scheduling is disclosed. The apparatus includes logic to store barrier usage data based on a magnitude of barrier messages in an application kernel and a scheduler to schedule execution of threads across a plurality of multiprocessors based on the barrier usage data.

公开(公告)号：US20200272215A1

公开(公告)日：2020-08-27

申请号：US16805480

申请日：2020-02-28

Applicant: INTEL CORPORATION

Inventor： Altug Koker ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Balaji Vembu ,  Prasoonkumar Surti ,  Kamal Sinha ,  Eric J. Hoekstra ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Travis T. Schluessler ,  Ankur N. Shah ,  Jonathan Kennedy

IPC: G06F1/3209 ,  H04W52/02 ,  G06F1/324 ,  G06F1/3203 ,  G06F1/3212 ,  G06F1/3218 ,  G06F1/3231 ,  G06F3/01 ,  G06F11/07 ,  G06F11/30

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200183849A1

公开(公告)日：2020-06-11

申请号：US16702073

申请日：2019-12-03

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  David Puffer ,  Prasoonkumar Surti ,  Lakshminarayanan Striramassarma ,  Vasanth Ranganathan ,  Kiran C. Veernapu ,  Balaji Vembu ,  Pattabhiraman K

IPC: G06F12/0877 ,  G06T1/60 ,  G06F12/0868 ,  G06F12/0846 ,  G06F12/0806 ,  G06F12/0855 ,  G06F12/0802 ,  G06F12/126

Abstract: In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.

公开(公告)号：US10672175B2

公开(公告)日：2020-06-02

申请号：US15489177

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Devan Burke ,  Adam T. Lake ,  Jeffery S. Boles ,  John H. Feit ,  Karthik Vaidyanathan ,  Abhishek R. Appu ,  Joydeep Ray ,  Subramaniam Maiyuran ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Gabor Liktor ,  Jonathan Kennedy ,  Slawomir Grajewski ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06T15/00 ,  G06F9/48 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10 ,  G06T17/20

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

公开(公告)号：US10579382B2

公开(公告)日：2020-03-03

申请号：US15879416

申请日：2018-01-24

Applicant: Intel Corporation

Inventor： Rajesh Sankaran ,  Ankur Shah ,  Bryan White ,  Hema Nalluri ,  David Puffer ,  Murali Ramadoss ,  Altug Koker ,  Aditya Navale ,  Balaji Vembu

IPC: G06F9/30 ,  G06F9/32 ,  G06T1/20 ,  G06F12/1009

Abstract: An apparatus and method for scalable interrupt reporting. For example, one embodiment of an apparatus comprises: a host processor to execute one or more processes having a corresponding one or more process contexts associated therewith; and a graphics processing engine to, upon initiating execution of a first process, determine a current process context associated with the first process including a first pointer to a first system memory region to store an interrupt status, a second pointer to a second system memory region to store interrupt enable and/or interrupt mask data for one or more interrupt events, and address/data values associated with a message signaled interrupt (MSI); the graphics processing engine, in response to an interrupt event, to evaluate the interrupt enable data from the second system memory region to determine whether the interrupt event is enabled, to report the interrupt event, if enabled, by writing a specified value to the first system memory region identified by the first pointer, and to generate a first MSI corresponding to the interrupt event by writing the MSI address/data values to an output accessible by the host processor.

公开(公告)号：US10565671B2

公开(公告)日：2020-02-18

申请号：US15495956

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Nikos Kaburlasos ,  Josh B. Mastronarde

IPC: G06T1/20 ,  G06T1/60 ,  G06F1/32 ,  G06F1/3234

Abstract: In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive an input from one or more detectors proximate a display to present an output from a graphics pipeline, determine that a user is not interacting with the display, and in response to a determination that the user is not interacting with the display, to reduce a frame rendering rate of the graphics pipeline. Other embodiments are also disclosed and claimed.

公开(公告)号：US10565354B2

公开(公告)日：2020-02-18

申请号：US15482514

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Abhishek R. Appu ,  Pattabhiraman K ,  Balaji Vembu ,  Altug Koker

IPC: G06F21/10 ,  G06F9/455 ,  G06F12/0815 ,  G06T15/00 ,  H04N19/00 ,  H04N21/4405

Abstract: An apparatus and method for protecting content in a graphics processor. For example, one embodiment of an apparatus comprises: encode/decode circuitry to decode protected audio and/or video content to generate decoded audio and/or video content; a graphics cache of a graphics processing unit (GPU) to store the decoded audio and/or video content; first protection circuitry to set a protection attribute for each cache line containing the decoded audio and/or video data in the graphics cache; a cache coherency controller to generate a coherent read request to the graphics cache; second protection circuitry to read the protection attribute to determine whether the cache line identified in the read request is protected, wherein if it is protected, the second protection circuitry to refrain from including at least some of the data from the cache line in a response.