公开(公告)号：US20230101038A1

公开(公告)日：2023-03-30

申请号：US17489741

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Patrick J. Shyvers

IPC: G06F12/0891 ,  G06F12/02 ,  G06F3/06 ,  G06F1/08

Abstract: A method and processing device for accessing data is provided. The processing device comprises a cache and a processor. The cache comprises a first data section having a first cache hit latency and a second data section having a second cache hit latency that is different from the first cache hit latency of the first data section. The processor is configured to request access to data in memory, the data corresponding to a memory address which includes an identifier that identifies the first data section of the cache. The processor is also configured to load the requested data, determined to be located in the first data section of the cache, according to the first cache hit latency of the first data section of the cache.

公开(公告)号：US20230100491A1

公开(公告)日：2023-03-30

申请号：US17487929

申请日：2021-09-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： PENG LI ,  CHANGWEI LIANG

IPC: H01R12/88

Abstract: A socket actuation mechanism for package insertion and package-socket alignment, including: a socket frame comprising a plurality of first hinge portions; a carrier frame comprising: a center portion comprising one or more package interlocks; and a tab extending from a first end of the carrier frame, the tab comprising a second hinge portion couplable with the plurality of first hinge portions to form a hinge coupling the carrier frame to the socket frame.

公开(公告)号：US20230100230A1

公开(公告)日：2023-03-30

申请号：US17488206

申请日：2021-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/0897 ,  G06F12/0864 ,  G06F12/123 ,  G06F12/02

Abstract: Systems and methods are disclosed for maintaining insertion policies of a lower-level cache. Techniques are described for selecting, based on metadata of an evicted data block received from an upper-level cache, an insertion policy out of the insertion policies. Then, determining, based on the selected insertion policy, whether to insert the data block into the lower-level cache. If it is determined to insert, the data block is inserted into the lower-level cache according to the selected insertion policy. Techniques for dynamically updating the insertion policies of the lower-level cache are also disclosed.

公开(公告)号：US20230098181A1

公开(公告)日：2023-03-30

申请号：US17485966

申请日：2021-09-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： CHRISTOPHER M. JAGGERS

IPC: H05K7/20 ,  G06F1/18

Abstract: A computing device chassis for a common cooling solution for die packages comprising: a chassis base comprising: an internal cavity; a cooling element housed in the internal cavity; and one or more thermal interfaces to the cooling element.

公开(公告)号：US20230096002A1

公开(公告)日：2023-03-30

申请号：US17890520

申请日：2022-08-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ranjith Kumar SAJJA ,  Sreekanth GODEY ,  Anirudh R. ACHARYA

IPC: G06F1/08 ,  G06F9/50 ,  G06F11/34 ,  G06F1/12

Abstract: Systems and methods related to controlling clock signals for clocking shader engines modules (SEs) and non-shader-engine modules (nSEs) of a graphics processing unit (GPU) are provided. One or more dividers receive a clock signal CLK and output a clock signal CLKA to the SEs and output a clock signal CLKB to the nSEs. The frequencies of CLKA and CLKB are independently selected based on sets of performance counter data monitored at the SEs and nSEs, respectively. The clock signal frequency for either the SEs or the nSEs is reduced when the corresponding sets of performance counter data indicates a comparatively lower processing workload for the SEs or for the nSEs.

公开(公告)号：US20230094384A1

公开(公告)日：2023-03-30

申请号：US17487103

申请日：2021-09-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： DMITRI TIKHOSTOUP ,  DANIEL WAIHIM WONG ,  WILLIAM HERZ

IPC: G06F9/50

Abstract: A dynamic allocator for providing platform resource candidates is disclosed. In an implementation, a platform resource allocator receives a request from a workload initiator such as, an application, for a platform resource recommendation. The platform resource allocator analyzes performance capabilities and utilization metrics of a plurality of platform resources for each of a plurality of resource. The plurality of platform resources includes one or more graphics processor units (GPUs) and one or more accelerated processing units (APUs). The platform resource allocator dynamically provides the platform resource recommendation to the workload initiator to select one or more of the plurality of platform resources to execute a workload based on the performance capabilities and utilization metrics.

公开(公告)号：US20230092184A1

公开(公告)日：2023-03-23

申请号：US17483672

申请日：2021-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/02

Abstract: A system and method for creating chip layout are described. In various implementations, a standard cell uses unidirectional tracks for power connections and signal routing. A single track of the metal one layer that uses a minimum width of the metal one layer is placed within a pitch of a single metal gate. The single track of the metal one layer provides a power supply reference voltage level or ground reference voltage level. This placement of the single track provides a metal one power post contacted gate pitch (CPP) of 1 CPP. To further reduce voltage droop, a standard cell uses dual height and half the width of a single height cell along with placing power posts with 1 CPP. The placement of the multiple power rails of the dual height cell allows alignment of the power rails with power rails of other standard cells.

公开(公告)号：US11604737B1

公开(公告)日：2023-03-14

申请号：US17516860

申请日：2021-11-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Joseph L. Greathouse ,  Steven Tony Tye ,  Mark Fowler ,  Milind N. Nemlekar

IPC: G06F12/00 ,  G06F12/0891 ,  G06F12/0831 ,  G06F9/448 ,  G06F9/30 ,  G06F12/0888

Abstract: A processing device determines a scope indicating at least a portion of the processing system and target data from atomic memory operation to be performed. Based on the scope, the processing device determines one or more hardware parameters for at least a portion of the processing system. The processing device then compares the hardware parameters to the scope and target data to determine one or more corrections. The processing device then provides the scope, target data, hardware parameters, and corrections to a plurality of hardware lookup tables. The hardware lookup tables are configured to receive the scope, target data, hardware parameters, and corrections as inputs and output values indicating one or more coherency actions and one or more orderings. The processing device then executes one or more of the indicated coherency actions and the atomic memory operation based on the indicated ordering.

公开(公告)号：US20230061698A1

公开(公告)日：2023-03-02

申请号：US18048689

申请日：2022-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Ngoc Vinh Vu ,  Neil Patrick Kelly

IPC: G01S13/89 ,  H04N7/20 ,  G01S7/00 ,  H04N5/38 ,  G01S7/04

Abstract: Systems, apparatuses, and methods for implementing a dual-purpose millimeter-wave frequency band transmitter are disclosed. A system includes a dual-purpose transmitter sending a video stream over a wireless link to a receiver. In some embodiments, the video stream is generated as part of an augmented reality (AR) or virtual reality (VR) application. The transmitter operates in a first mode to scan and map an environment of the transmitter and receiver. The transmitter generates radio frequency (RF) signals in a first frequency range while operating in the first mode. Additionally, the transmitter operates in a second mode to send video data to the receiver, and the transmitter generates RF signals in the first frequency range while operating in the second mode.

公开(公告)号：US11586563B2

公开(公告)日：2023-02-21

申请号：US17130604

申请日：2020-12-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Max Ruttenberg ,  Vendula Venkata Srikant Bharadwaj ,  Yasuko Eckert ,  Anthony Gutierrez ,  Mark H. Oskin

IPC: G06F13/16 ,  G11C11/4076

Abstract: A processor distributes memory timing parameters and data among different memory modules based upon memory access patterns. The memory access patterns indicate different types, or classes, of data for an executing workload, with each class associated with different memory access characteristics, such as different row buffer hit rate levels, different frequencies of access, different criticalities, and the like. The processor assigns each memory module to a data class and sets the memory timing parameters for each memory module according to the module's assigned data class, thereby tailoring the memory timing parameters for efficient access of the corresponding data.