公开(公告)号：US20100289949A1

公开(公告)日：2010-11-18

申请号：US12760511

申请日：2010-04-14

Applicant: Osamu Kobayashi

Inventor： Osamu Kobayashi

IPC: H04N11/06 ,  G06F13/38

CPC classification number: G06F13/385 ,  G06F13/4081 ,  H04L69/324 ,  H04N21/43632

Abstract: Methods and systems are described for transmitting and displaying video data after a hot plug event during a start-up dead period. In particular, hot plug events occurring when a toggleable hot plug detection mechanism is use.

Abstract translation: 描述了在启动死区期间在热插拔事件之后发送和显示视频数据的方法和系统。 特别地，当使用可切换热插拔检测机构时发生的热插拔事件。

公开(公告)号：US07825917B2

公开(公告)日：2010-11-02

申请号：US11390115

申请日：2006-03-27

Applicant: Frank R. Bryant ,  Frank J. Sigmund

Inventor： Frank R. Bryant ,  Frank J. Sigmund

IPC: G09G5/00 ,  H04B1/38 ,  H04M1/00

CPC classification number: G09G5/10 ,  G09G2320/0626 ,  G09G2320/066 ,  G09G2320/0666 ,  G09G2360/144

Abstract: An apparatus includes a display panel capable of displaying content. The apparatus also includes a light sensor having an integrated circuit and a photo-sensitive device. The photo-sensitive device is capable of measuring an amount of ambient light. The integrated circuit is capable of performing one or more functions associated with the display of the content on the display panel. The apparatus further includes a controller capable of adjusting one or more characteristics of the display panel based on the amount of ambient light measured by the light sensor. The integrated circuit and the photo-sensitive device may be formed on one side of a semiconductor wafer, and the photo-sensitive device may be exposed to the ambient light through an opening in an opposing side of the semiconductor wafer.

Abstract translation: 一种装置包括能够显示内容的显示面板。 该装置还包括具有集成电路和感光装置的光传感器。 感光装置能够测量环境光的量。 集成电路能够执行与显示面板上的内容的显示相关联的一个或多个功能。 该装置还包括能够基于由光传感器测量的环境光量来调整显示面板的一个或多个特性的控制器。 集成电路和感光器件可以形成在半导体晶片的一侧，并且光敏器件可以通过半导体晶片的相对侧中的开口暴露于环境光。

公开(公告)号：US07813318B2

公开(公告)日：2010-10-12

申请号：US11549895

申请日：2006-10-16

Applicant: Wendong Hu

Inventor： Wendong Hu

IPC: H04Q7/00 ,  H04B7/208

CPC classification number: H04W16/14 ,  H04B1/7183 ,  H04W74/08

Abstract: This invention relates to cognitive radio based wireless communications of dynamic spectrum access networks, and more particularly to a method of addressing messaging control for dynamic frequency selection. The method of the invention provides an efficient, reliable and flexible messaging mechanism for DFS decision-making that is critical for licensed incumbent protection and inter-system coexistence of dynamic spectrum access systems.

Abstract translation: 本发明涉及动态频谱接入网络的基于认知无线电的无线通信，更具体地涉及一种寻址用于动态频率选择的消息收发控制的方法。 本发明的方法为DFS决策提供了一种有效，可靠和灵活的消息传递机制，这对于许可的现任保护和动态频谱接入系统的系统间共存至关重要。

公开(公告)号：US20100246051A1

公开(公告)日：2010-09-30

申请号：US12751740

申请日：2010-03-31

Applicant: Ezio Galbiati ,  Frederic Pascal Bonvin

Inventor： Ezio Galbiati ,  Frederic Pascal Bonvin

IPC: G11B15/48

CPC classification number: G11B19/2063

Abstract: A method and circuit to stop a spindle motor in the absence of the external supply voltage in which the spindle motor is structured to move a hard disk provided with at least one reading or writing head moved by a voice coil motor, the spindle motor provided with a plurality of coils. The method includes rectifying the backelectromotive force of the spindle motor to produce a braking current, driving the voice coil motor with at least a portion of the braking current until the speed of the spindle motor becomes lower than a predetermined stop speed, and, after the parking of the at least one reading or writing head of the voice coil motor, stopping the spindle motor by short-circuiting the coils of the spindle motor.

Abstract translation: 一种在没有外部电源电压的情况下停止主轴电机的方法和电路，其中主轴电机被构造成移动设置有由音圈电机移动的至少一个读/写头的硬盘， 多个线圈。 该方法包括整流主轴电动机的反电动势以产生制动电流，以至少一部分制动电流驱动音圈电动机，直到主轴电动机的速度变得低于预定的停止速度，并且在 停放音圈电动机的至少一个读写头，通过使主轴电动机的线圈短路来停止主轴电动机。

公开(公告)号：US07800446B2

公开(公告)日：2010-09-21

申请号：US12378520

申请日：2009-02-17

Applicant: Christopher Yong

Inventor： Christopher Yong

IPC: H03F3/45

CPC classification number: H03F3/4508 ,  H03F3/3432 ,  H03F3/45475 ,  H03F2200/375 ,  H03F2200/393 ,  H03F2200/447 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2203/45101 ,  H03F2203/45136 ,  H03G7/08

Abstract: A method for varying gain exponentially with respect to a control signal is provided. The method includes receiving a primary control signal. A secondary control signal is generated based on the primary control signal. The secondary control signal is provided to a variable gain amplifier and is operable to exponentially vary a gain for the variable gain amplifier with respect to the primary control signal.

Abstract translation: 提供了一种相对于控制信号以指数方式改变增益的方法。 该方法包括接收主控制信号。 基于主控制信号产生辅助控制信号。 次级控制信号被提供给可变增益放大器，并且可操作以相对于主控制信号指数地改变可变增益放大器的增益。

公开(公告)号：US07779236B1

公开(公告)日：2010-08-17

申请号：US09443160

申请日：1999-11-19

Applicant: David L. Isaman

Inventor： David L. Isaman

IPC: G06F9/40

CPC classification number: G06F9/3832 ,  G06F9/355 ,  G06F9/3826 ,  G06F9/3834 ,  G06F12/0855

Abstract: The invention provides a method and system for operating a pipelined microprocessor more quickly, by detecting instructions that load from identical memory locations as were recently stored to, without having to actually compute the referenced external memory addresses. The microprocessor examines the symbolic structure of instructions as they are encountered, so as to be able to detect identical memory locations by examination of their symbolic structure. For example, in a preferred embodiment, instructions that store to and load from an identical offset from an identical register are determined to be referencing the identical memory location, without having to actually compute the complete physical target address.

Abstract translation: 本发明通过检测从最近存储的相同存储器位置加载的指令，而不必实际计算所引用的外部存储器地址，从而提供了一种更快地操作流水线微处理器的方法和系统。 微处理器检查指令的符号结构，以便能够通过检查其符号结构来检测相同的存储器位置。 例如，在优选实施例中，确定存储到相同寄存器的相同偏移量并从相同寄存器加载的指令参考相同的存储器位置，而不必实际计算完整的物理目标地址。

公开(公告)号：US07777753B2

公开(公告)日：2010-08-17

申请号：US12424389

申请日：2009-04-15

Applicant: Jefferson Eugene Owen ,  Raul Zegers Diaz ,  Osvaldo Colavin

Inventor： Jefferson Eugene Owen ,  Raul Zegers Diaz ,  Osvaldo Colavin

IPC: G06F15/167 ,  G09G5/36 ,  G09G5/39

CPC classification number: G06T1/60 ,  G06F13/1605 ,  G06F13/18 ,  G06F15/167 ,  G09G5/001 ,  G09G5/363 ,  G09G2340/02 ,  G09G2360/18 ,  H04N19/423 ,  H04N19/427 ,  H04N19/61 ,  H04N21/443 ,  H04N21/4435

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract translation: 公开了电子系统，集成电路和显示方法。 电子系统包含第一设备，存储器以及诸如解码器/编码器的视频/音频压缩/解压缩设备。 电子系统被配置为允许第一设备和视频/音频压缩/解压缩设备共享存储器。 电子系统可以包括在计算机中，在这种情况下，存储器是主存储器。 存储器访问由一个或多个存储器接口实现，存储器直接耦合到总线，或者将第一设备和解码器/编码器直接耦合到总线。 仲裁器基于优先级选择性地提供对存储器的第一设备和/或解码器/编码器的访问。 仲裁器可以单片地集成到存储器接口中。 解码器可以是被配置为符合MPEG-2标准的视频解码器。 存储器可以存储从前一图像获得的预测图像。

公开(公告)号：US07774767B2

公开(公告)日：2010-08-10

申请号：US11347108

申请日：2006-02-03

Applicant: Michael J. Wolfe

Inventor： Michael J. Wolfe

IPC: G06F9/45

CPC classification number: G06F8/71 ,  G06F8/443

Abstract: A method includes extracting at least one object file from a library of object files. The method also includes identifying an interprocedural optimization associated with a plurality of object files. The plurality of object files includes the at least one extracted object file. The method further includes invoking recompilation of at least one of the plurality of object files to implement the identified interprocedural optimization. In addition, the method includes generating at least one executable file using the at least one recompiled object file. The plurality of object files could include interprocedural summary information generated by a compiler during a compilation of at least one source file and a compiler internal representation associated with the compiler during the compilation. The interprocedural optimization could be identified using the interprocedural summary information, and the at least one recompiled object file could be generated using the compiler internal representation.

Abstract translation: 一种方法包括从目标文件库提取至少一个目标文件。 该方法还包括识别与多个目标文件相关联的过程间优化。 多个对象文件包括至少一个提取的目标文件。 该方法还包括调用多个对象文件中的至少一个的重新编译以实现所识别的过程间优化。 此外，该方法包括使用至少一个重新编译的目标文件生成至少一个可执行文件。 多个对象文件可以包括在编译期间编译期间由编译器生成的过程内摘要信息，该编译器在汇编期间编译与编译器相关联的至少一个源文件和编译器内部表示。 可以使用过程间摘要信息来识别过程间优化，并且可以使用编译器内部表示来生成至少一个重新编译的对象文件。

公开(公告)号：US07768732B2

公开(公告)日：2010-08-03

申请号：US11402155

申请日：2006-04-10

Applicant: Hakan Ozdemir

Inventor： Hakan Ozdemir

IPC: G11B5/035

CPC classification number: G11B5/09 ,  G11B20/10009

Abstract: A gain controller for a gain loop of a read channel includes a comparator circuit, an accumulator circuit, and a function circuit. The comparator circuit determines an error between an actual sample of a read signal and a corresponding ideal sample of the read signal, and the accumulator circuit holds a gain-correction value and adjusts the gain-correction value in response to the error. The function circuit generates a gain-correction signal by performing a predetermined mathematical operation involving the gain-correction value, and provides the gain-correction signal to a variable-gain amplifier that is operable to amplify actual samples of the read signal. Because such a gain controller allows one to locate the variable-gain amplifier (VGA) after the analog-to-digital converter (ADC) in a read channel, the gain controller may significantly reduce the latency of the gain-acquisition (GA) loop or the gain-tracking (GT) loop of the read channel. The gain controller may also allow the GA loop and the GT loop to be completely contained with in the digital portion of the read channel.

Abstract translation: 用于读通道的增益环的增益控制器包括比较器电路，累加器电路和功能电路。 比较器电路确定读取信号的实际样本与读取信号的对应理想采样之间的误差，并且累加器电路保持增益校正值并响应于该误差调整增益校正值。 功能电路通过执行涉及增益校正值的预定数学运算来生成增益校正信号，并将增益校正信号提供给可操作以放大读取信号的实际采样的可变增益放大器。 因为这样的增益控制器允许在读通道中的模数转换器（ADC）之后定位可变增益放大器（VGA），所以增益控制器可以显着降低增益采集（GA）回路的延迟 或读通道的增益跟踪（GT）循环。 增益控制器还可以允许GA循环和GT循环在读取通道的数字部分中被完全包含。

公开(公告)号：US07757066B2

公开(公告)日：2010-07-13

申请号：US09751372

申请日：2000-12-29

Applicant: Anthony X. Jarvis ,  Paolo Faraboschi

Inventor： Anthony X. Jarvis ,  Paolo Faraboschi

IPC: G06F9/30

CPC classification number: G06F9/3867 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3885 ,  G06F9/3891 ,  G06F12/0855

Abstract: There is disclosed a data processor that executes variable latency load operations using bypass circuitry that allows load word operations to avoid stalls caused by shifting circuitry. The processor comprises: 1) an instruction execution pipeline comprising N processing stages, each of the N processing stages for performing one of a plurality of execution steps associated with a pending instruction being executed by the instruction execution pipeline; 2) a data cache for storing data values used by the pending instruction; 3) a plurality of registers for receiving the data values from the data cache; 4) a load store unit for transferring a first one of the data values from the data cache to a target one of the plurality of registers during execution of a load operation; 5) a shifter circuit associated with the load store unit for shifting the first data value prior to loading the first data value into the target register; and 6) bypass circuitry associated with the load store unit for transferring the first data value from the data cache directly to the target register without processing the first data value in the shifter circuit.

Abstract translation: 公开了一种使用旁路电路执行可变等待时间负载操作的数据处理器，其允许加载字操作以避免由移位电路引起的停顿。 所述处理器包括：1）包括N个处理级的指令执行流水线，所述N个处理级中的每一个执行与由所述指令执行管线执行的待决指令相关联的多个执行步骤之一; 2）用于存储待决指令使用的数据值的数据高速缓存; 3）用于从数据高速缓存接收数据值的多个寄存器; 4）一种加载存储单元，用于在执行加载操作期间将数据值中的第一个数据值从数据高速缓存传送到多个寄存器中的目标寄存器; 5）与加载存储单元相关联的移位器电路，用于在将第一数据值加载到目标寄存器之前移位第一数据值; 和6）旁路与加载存储单元相关联的电路，用于将第一数据值从数据高速缓存直接传送到目标寄存器，而不处理移位器电路中的第一数据值。