公开(公告)号：US06696725B1

公开(公告)日：2004-02-24

申请号：US09527227

申请日：2000-03-16

Applicant: Judy X. An ,  Bin Yu

Inventor： Judy X. An ,  Bin Yu

IPC: H01L31119

CPC classification number: H01L29/66484 ,  H01L21/28105 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/7831

Abstract: A semiconductor device with reduced hot carrier injection and punch through is formed with a dual gate electrode comprising edge conductive portions, a central conductive portion, and dielectric sidewall spacers formed between the edge conductive portions and central conductive portion. The edge conductive portions provide high potential barriers against the active regions, thereby reducing threshold voltage roll off and leakage current.

Abstract translation: 具有减少的热载流子注入和穿通的半导体器件由双栅极电极形成，该双栅电极包括边缘导电部分，中心导电部分和形成在边缘导电部分和中心导电部分之间的电介质侧壁间隔物。 边缘导电部分提供抵抗有源区域的高电势势垒，从而降低阈值电压滚降和漏电流。

公开(公告)号：US06670260B1

公开(公告)日：2003-12-30

申请号：US09577332

申请日：2000-05-24

Applicant: Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

Inventor： Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

IPC: H01L21425

CPC classification number: H01L29/6659 ,  H01L29/0649 ,  H01L29/78

Abstract: A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field defect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

Abstract translation: 薄膜完全耗尽的绝缘体上硅（SOI）金属氧化物半导体场缺陷晶体管（MOSFET）利用局部绝缘结构。 局部绝缘结构包括沟道区下方的埋置二氧化硅区域。 MOSFET体的厚度非常小，而在沟道区域和掩埋的二氧化硅区域之外可用的硅可用于源极和漏极区域中足够的硅化物深度。 掩埋的二氧化硅区域可以通过沟槽隔离技术或LOCOS技术形成。

公开(公告)号：US06630386B1

公开(公告)日：2003-10-07

申请号：US09618857

申请日：2000-07-18

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/324 ,  H01L29/1083 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659

Abstract: A method of manufacturing an integrated circuit may include the steps of annealing a gate structure and a halo section disposed over a substrate using a first temperature, implanting dopants to form drain and source regions, and annealing drain and source regions at a second temperature. The second temperature is substantially less than the first temperature.

Abstract translation: 制造集成电路的方法可以包括以下步骤：使用第一温度退火设置在衬底上的栅极结构和卤素区段，注入掺杂剂以形成漏极和源极区域，以及在第二温度下退火漏极和源极区域。 第二温度基本上小于第一温度。

公开(公告)号：US06562665B1

公开(公告)日：2003-05-13

申请号：US09688903

申请日：2000-10-16

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2184

CPC classification number: H01L29/7853 ,  H01L29/42384 ,  H01L29/66795

Abstract: For fabricating a field effect transistor, a pillar of semiconductor material is formed, a recess is formed in the top surface of the pillar along the length of the pillar, a gate dielectric material is deposited on any exposed surface of the semiconductor material of the pillar including at the top surface and the first and second side surfaces of the pillar and at the sidewalls and the bottom wall of the recess, for a gate length along the length of the pillar. In addition, a gate electrode material is deposited on the gate dielectric material to surround the pillar at the top surface and the first and second side surfaces of the pillar and to fill the recess, for the gate length of the pillar. A drain and source dopant is implanted into exposed regions of the pillar to form a drain of the field effect transistor on a first side of the gate electrode material along the length of the pillar and to form a source of the field effect transistor on a second side of the gate electrode material along the length of the pillar.

Abstract translation: 为了制造场效应晶体管，形成半导体材料的柱，沿着柱的长度在柱的上表面形成凹部，栅极电介质材料沉积在柱的半导体材料的任何暴露的表面上 包括在柱的顶表面和柱的第一和第二侧表面以及凹槽的侧壁和底壁处，用于沿着柱的长度的浇口长度。 此外，栅极电极材料沉积在栅极电介质材料上，以围绕柱的上表面和柱的第一和第二侧表面处的柱，并填充凹槽以用于柱的栅极长度。 将漏极和源极掺杂剂注入到柱的暴露区域中，以在栅极电极材料的沿着该柱的长度的第一侧上形成场效应晶体管的漏极，并在第二个栅极晶体管的一端形成一个源极 沿着柱的长度的栅电极材料的侧面。

公开(公告)号：US06551886B1

公开(公告)日：2003-04-22

申请号：US09844637

申请日：2001-04-27

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66772 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66545

Abstract: An ultra-thin body SOI MOSFET transistor and fabrication method are described which provide extended silicide depth in a gate-last process. The method utilizes the fabrication of a dummy gate, comprising insulation, which is replaced with an insulated gate after implantation, annealing, and the formation of silicide so that diffusion effects are reduced. By way of example, dummy gate stacks are created having insulating upper segments. Silicon is deposited on the wafer and planarized to expose the insulating segment. The junction is formed by implantation followed by annealing to recrystallize the silicon and to activate the junction. Silicide is then formed, to a depth which can exceed the thickness of the silicon within the SOI wafer, on the upper portion of the silicon layer. The segment of insulation is then removed and a gate is formed with a gate electrode insulated by high-k dielectric.

Abstract translation: 描述了一种超薄体SOI MOSFET晶体管和制造方法，其在栅极最后工艺中提供延长的硅化物深度。 该方法利用伪栅的制造，包括绝缘，其在植入，退火和硅化物的形成之后被绝缘栅取代，使得扩散效应降低。 作为示例，制造具有绝缘上段的虚拟栅极堆叠。 硅沉积在晶片上并平坦化以暴露绝缘段。 通过注入形成结，然后进行退火以使硅重结晶并激活连接。 然后，在硅层的上部形成硅化物，其深度可以超过SOI晶片内的硅的厚度。 然后去除绝缘区段，并且形成具有由高k电介质绝缘的栅电极的栅极。

公开(公告)号：US06531710B1

公开(公告)日：2003-03-11

申请号：US09853342

申请日：2001-05-10

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2904

CPC classification number: H01L21/02686 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2026 ,  H01L21/76264 ,  H01L21/76283

Abstract: An ULSI MOSFET formed using silicon on insulator (SOI) principles includes masking regions of an amorphous silicon film on a substrate and exposing intended active regions. Laser energy is directed against the intended active regions to anneal these regions without annealing the masked regions, thereby increasing production throughput and decreasing defect density.

Abstract translation: 使用绝缘体上硅（SOI）原理形成的ULSI MOSFET包括在衬底上的非晶硅膜的掩蔽区域并暴露预期的有源区域。 激光能量针对预期的有源区域进行退火以退火这些区域而不对掩蔽区域进行退火，由此增加生产量并降低缺陷密度。

公开(公告)号：US06528851B1

公开(公告)日：2003-03-04

申请号：US09871191

申请日：2001-05-31

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2701

CPC classification number: H01L29/66772 ,  H01L29/458 ,  H01L29/78612 ,  H01L29/78621

Abstract: A semiconductor-on-insulator (SOI) transistor is disclosed. The SOI transistor includes a source region, a drain region and a body region disposed therebetween, the body region including a gate disposed thereon, the source and drain regions including respective silicide regions. The body region includes a region of recombination centers formed by atom implantation, wherein atoms forming the region of recombination centers are implanted at an angle from opposite sides of the gate in a direction towards the body region, with the gate and source and drain silicide regions acting as an implant blocking mask, such that the region of recombination centers is disposed between a source/body junction and a drain/body junction. Also disclosed is a method of fabricating the SOI transistor.

Abstract translation: 公开了一种绝缘体上半导体（SOI）晶体管。 SOI晶体管包括源极区域，漏极区域和设置在其间的体区域，所述体区域包括设置在其上的栅极，源区域和漏极区域包括各自的硅化物区域。 身体区域包括通过原子注入形成的复合中心区域，其中形成复合中心区域的原子沿着朝向身体区域的方向从栅极的相对侧以一定角度注入，栅极和源极和漏极硅化物区域 充当植入物阻挡掩模，使得复合中心区域设置在源极/主体结与漏极/主体结之间。 还公开了制造SOI晶体管的方法。

公开(公告)号：US06521501B1

公开(公告)日：2003-02-18

申请号：US09310170

申请日：1999-05-11

Applicant: Jeff Erhardt ,  Bin Yu ,  G. Jonathan Kluth

Inventor： Jeff Erhardt ,  Bin Yu ,  G. Jonathan Kluth

IPC: H01L21336

CPC classification number: H01L29/6653 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/324 ,  H01L29/6659

Abstract: A method of forming a CMOS structure, the method including the acts of: forming a gate structure over a substrate layer; forming a silicide layer over the substrate layer; forming shallow source/drain areas in the substrate layer; forming an oxide diffusion barrier layer over the structure; forming a metal absorption layer over the oxide diffusion barrier layer; and melting portions of the substrate layer directly overlying the shallow source/drain areas, thereby transforming the shallow source/drain areas into shallow source/drain regions. The act of melting includes the act of exposing the metal absorption layer to pulsed laser beams.

Abstract translation: 一种形成CMOS结构的方法，所述方法包括以下动作：在衬底层上形成栅极结构; 在衬底层上形成硅化物层; 在衬底层中形成浅的源极/漏极区域; 在所述结构上形成氧化物扩散阻挡层; 在所述氧化物扩散阻挡层上形成金属吸收层; 并且将衬底层的部分直接覆盖在浅源极/漏极区域上，从而将浅的源极/漏极区域变换成浅的源极/漏极区域。 熔化的行为包括将金属吸收层暴露于脉冲激光束的行为。

公开(公告)号：US06518631B1

公开(公告)日：2003-02-11

申请号：US09824418

申请日：2001-04-02

Applicant: William G. En ,  Srinath Krishnan ,  Dong-Hyuk Ju ,  Bin Yu

Inventor： William G. En ,  Srinath Krishnan ,  Dong-Hyuk Ju ,  Bin Yu

IPC: H01L31113

CPC classification number: H01L29/6653 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78621

Abstract: A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a plurality of thin silicide layers formed on the source and the drain. Additionally, at least an upper silicide layer of the plurality of thin silicide layers extends beyond a lower silicide layer. Further still, the device includes a plurality of spacers used in the formation of the device. The device further includes a second plurality of thin silicide layers formed on a polysilicon electrode of the gate.

Abstract translation: 一种在绝缘体上半导体（SOI）衬底上形成的埋置氧化物（BOX）层的晶体管器件，以及设置在具有由隔离沟槽限定的有源区域的BOX层上的有源层。 该器件包括限定插入在SOI衬底的有源区域内形成的源极和漏极之间的沟道的栅极。 此外，该器件包括形成在源极和漏极上的多个薄硅化物层。 另外，多个薄硅化物层中的至少一个上硅化物层延伸超过下硅化物层。 此外，该装置还包括用于形成装置的多个间隔物。 该器件还包括形成在栅极的多晶硅电极上的第二多个薄硅化物层。

公开(公告)号：US06504214B1

公开(公告)日：2003-01-07

申请号：US10044246

申请日：2002-01-11

Applicant: Bin Yu ,  Qi Xiang

Inventor： Bin Yu ,  Qi Xiang

IPC: H01L2978

CPC classification number: H01L21/28194 ,  H01L21/2807 ,  H01L29/41783 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628

Abstract: A MOSFET device and method of fabrication. The MOSFET includes a gate having a gate electrode and a gate dielectric formed from a high-K material, the gate dielectric separating the gate electrode and a layer of semiconductor material. A source and a drain each formed by selective in-situ doped epitaxy and located adjacent opposite sides of the gate so as to define a body region from the layer of semiconductor material between the source and the drain and under the gate.

Abstract translation: 一种MOSFET器件及其制造方法。 MOSFET包括具有栅极电极和由高K材料形成的栅极电介质的栅极，栅极电介质分离栅电极和半导体材料层。 源极和漏极各自由选择性原位掺杂外延形成并且位于栅极的相邻相对侧，以便在源极和漏极之间以及在栅极之下限定半导体材料层的主体区域。