公开(公告)号：US06521501B1

公开(公告)日：2003-02-18

申请号：US09310170

申请日：1999-05-11

Applicant: Jeff Erhardt ,  Bin Yu ,  G. Jonathan Kluth

Inventor： Jeff Erhardt ,  Bin Yu ,  G. Jonathan Kluth

IPC: H01L21336

CPC classification number: H01L29/6653 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/324 ,  H01L29/6659

Abstract: A method of forming a CMOS structure, the method including the acts of: forming a gate structure over a substrate layer; forming a silicide layer over the substrate layer; forming shallow source/drain areas in the substrate layer; forming an oxide diffusion barrier layer over the structure; forming a metal absorption layer over the oxide diffusion barrier layer; and melting portions of the substrate layer directly overlying the shallow source/drain areas, thereby transforming the shallow source/drain areas into shallow source/drain regions. The act of melting includes the act of exposing the metal absorption layer to pulsed laser beams.

Abstract translation: 一种形成CMOS结构的方法，所述方法包括以下动作：在衬底层上形成栅极结构; 在衬底层上形成硅化物层; 在衬底层中形成浅的源极/漏极区域; 在所述结构上形成氧化物扩散阻挡层; 在所述氧化物扩散阻挡层上形成金属吸收层; 并且将衬底层的部分直接覆盖在浅源极/漏极区域上，从而将浅的源极/漏极区域变换成浅的源极/漏极区域。 熔化的行为包括将金属吸收层暴露于脉冲激光束的行为。

公开(公告)号：US06518631B1

公开(公告)日：2003-02-11

申请号：US09824418

申请日：2001-04-02

Applicant: William G. En ,  Srinath Krishnan ,  Dong-Hyuk Ju ,  Bin Yu

Inventor： William G. En ,  Srinath Krishnan ,  Dong-Hyuk Ju ,  Bin Yu

IPC: H01L31113

CPC classification number: H01L29/6653 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78621

Abstract: A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a plurality of thin silicide layers formed on the source and the drain. Additionally, at least an upper silicide layer of the plurality of thin silicide layers extends beyond a lower silicide layer. Further still, the device includes a plurality of spacers used in the formation of the device. The device further includes a second plurality of thin silicide layers formed on a polysilicon electrode of the gate.

Abstract translation: 一种在绝缘体上半导体（SOI）衬底上形成的埋置氧化物（BOX）层的晶体管器件，以及设置在具有由隔离沟槽限定的有源区域的BOX层上的有源层。 该器件包括限定插入在SOI衬底的有源区域内形成的源极和漏极之间的沟道的栅极。 此外，该器件包括形成在源极和漏极上的多个薄硅化物层。 另外，多个薄硅化物层中的至少一个上硅化物层延伸超过下硅化物层。 此外，该装置还包括用于形成装置的多个间隔物。 该器件还包括形成在栅极的多晶硅电极上的第二多个薄硅化物层。

公开(公告)号：US06479868B1

公开(公告)日：2002-11-12

申请号：US09845659

申请日：2001-04-30

Applicant: Xilin Judy An ,  Bin Yu ,  Concetta E. Riccobene

Inventor： Xilin Judy An ,  Bin Yu ,  Concetta E. Riccobene

IPC: H01L2701

CPC classification number: H01L29/66772 ,  H01L29/78612 ,  H01L29/78624 ,  H01L29/78684

Abstract: A silicon-on-insulator (SOI) transistor. The SOI transistor includes a germanium implanted source and drain having a body disposed therebetween, and a gate disposed on the body, the germanium being implanted at an angle such that the source has a concentration of germanium at a source/body junction and the gate shields germanium implantation in the drain adjacent a drain/body junction resulting in a graduated drain/body junction. Also disclosed is a method of fabricating the SOI transistor.

Abstract translation: 绝缘体上硅（SOI）晶体管。 SOI晶体管包括锗注入源和漏极，其中设置有一个主体，以及设置在主体上的栅极，以一定角度注入锗，使得源在源极/主体结处具有锗的浓度，栅极屏蔽 在排水管/主体连接处的漏极中进行锗注入，导致刻度的漏极/体结。 还公开了制造SOI晶体管的方法。

公开(公告)号：US06472282B1

公开(公告)日：2002-10-29

申请号：US09639380

申请日：2000-08-15

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/26513 ,  H01L29/7833

Abstract: A method of manufacturing an integrated circuit may include the steps of forming a deep amorphous region and doping the deep amorphous region. The doping of the deep amorphous region can form source and drain regions with extensions. After doping, the substrate is annealed. The annealing can occur at a low temperature. The deep amorphous region can be formed with a self-amorphizing implant.

Abstract translation: 制造集成电路的方法可以包括形成深非晶区域并掺杂深非晶区域的步骤。 深非晶区域的掺杂可以形成具有延伸的源极和漏极区域。 掺杂后，将基板退火。 退火可以在低温下进行。 深非晶区域可以用自身非晶化植入物形成。

公开(公告)号：US06465315B1

公开(公告)日：2002-10-15

申请号：US09476527

申请日：2000-01-03

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/1045 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586

Abstract: A method of fabricating an integrated circuit with a source side compensation implant utilizes tilt-angle implants. An asymmetric channel profile is formed in which less dopants are located on a source side. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).

Abstract translation: 使用源极侧补偿注入制造集成电路的方法利用倾斜角植入。 形成非对称沟道轮廓，其中较少的掺杂剂位于源侧。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。

公开(公告)号：US06455903B1

公开(公告)日：2002-09-24

申请号：US09491267

申请日：2000-01-26

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2976

CPC classification number: H01L21/823807 ,  H01L21/26506 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76283 ,  H01L29/0649

Abstract: An integrated circuit and method of fabricating integrated circuits is provided for an integrated circuit having threshold voltage adjustment. Unlike conventional methods and devices, threshold voltage adjustment is provided by an inert ion implantation process whereby inert ions are implanted into an underlying substrate. The implantation forms a semi-insulative layer comprised of an accumulation of inert ions. The inert ion region is formed between source and drain regions of a device on the integrated circuit. During operation of the device, the accumulation region confines the depth of the depletion layer. By confining the depth of the depletion layer, the threshold voltage of the device is reduced.

Abstract translation: 为具有阈值电压调整的集成电路提供集成电路和制造集成电路的方法。 与常规方法和装置不同，通过惰性离子注入工艺提供阈值电压调节，由此将惰性离子注入到下面的衬底中。 注入形成由惰性离子的积聚组成的半绝缘层。 惰性离子区域形成在集成电路上的器件的源极和漏极区域之间。 在装置运行期间，积聚区域限制耗尽层的深度。 通过限制耗尽层的深度，器件的阈值电压降低。

公开(公告)号：US06451644B1

公开(公告)日：2002-09-17

申请号：US09187618

申请日：1998-11-06

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L218234

CPC classification number: H01L21/2807 ,  H01L21/268 ,  H01L21/28052 ,  H01L21/28061 ,  H01L29/4916

Abstract: An ultra-large scale integrated (ULSI) circuit includes MOSFETs which have a gate conductor with dopants distributed in a box-like distribution. The dopants also achieve high electrical activation. The MOSFETs utilize gate structures with heavily doped polysilicon material or heavily doped polysilicon and germanium material. The polysilicon and polysilicon and germanium materials are manufactured by utilizing amorphous semiconductor layers. Excimer laser annealing is utilized to activate the dopants and to provide a box-like dopant profile.

Abstract translation: 超大规模集成（ULSI）电路包括具有分布在盒状分布中的掺杂剂的栅极导体的MOSFET。 掺杂剂也可实现高电活化。 MOSFET利用具有重掺杂多晶硅材料或重掺杂多晶硅和锗材料的栅极结构。 通过利用非晶半导体层制造多晶硅和多晶硅和锗材料。 使用准分子激光退火来激活掺杂剂并提供盒状掺杂物分布。

公开(公告)号：US06448613B1

公开(公告)日：2002-09-10

申请号：US09846958

申请日：2001-05-01

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L27148

CPC classification number: H01L21/28052 ,  H01L21/26586 ,  H01L21/28105 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6659 ,  Y10S977/707

Abstract: A field effect transistor is fabricated to have a drain overlap and a source overlap to minimize series resistance between the gate and the drain and between the gate and the source of the field effect transistor. The parasitic Miller capacitance formed by the drain overlap and the source overlap is reduced by forming a depletion region at the sidewalls of the gate structure of the field effect transistor. The depletion region at the sidewalls of the gate structure is formed by counter-doping the sidewalls of the gate structure. The sidewalls of the gate structure at the drain side and the source side of the field effect transistor are doped with a type of dopant that is opposite to the type of dopant within the gate structure. Such dopant at the sidewalls of the gate structure forms a respective depletion region from the sidewall into approximately the edge of the drain overlap and source overlap that extends under the gate structure to reduce the parasitic Miller capacitance formed by the drain overlap and the source overlap.

Abstract translation: 制造场效应晶体管以具有漏极重叠和源重叠，以使栅极和漏极之间以及场效应晶体管的栅极和源极之间的串联电阻最小化。 通过在场效应晶体管的栅极结构的侧壁处形成耗尽区，减少由漏极重叠和源极重叠形成的寄生米勒电容。 通过对栅极结构的侧壁进行反掺杂来形成栅极结构的侧壁处的耗尽区。 在场效应晶体管的漏极侧和源极侧的栅极结构的侧壁掺杂有与栅极结构内的掺杂剂类型相反的掺杂剂。 在栅极结构的侧壁处的这种掺杂剂从侧壁形成相应的耗尽区，从而在栅极结构下延伸的漏极重叠和源极重叠的大致边缘，以减小由漏极重叠和源极重叠形成的寄生米勒电容。

公开(公告)号：US06445042B1

公开(公告)日：2002-09-03

申请号：US09687992

申请日：2000-10-13

Applicant: Bin Yu ,  Judy Xilin An

Inventor： Bin Yu ,  Judy Xilin An

IPC: H01L2976

CPC classification number: H01L29/6659 ,  G01N21/9501 ,  G01R31/307 ,  G01R31/311 ,  H01J37/21 ,  H01J2237/2817 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834 ,  Y10S257/90 ,  Y10S977/869 ,  Y10S977/881 ,  Y10S977/901 ,  Y10S977/954

Abstract: An improved semiconductor device, such as a MOSFET with raised source/drain extensions on a substrate with isolation trenches etched into the surface of the substrate . The device has thin first dielectric spacers on the side of a gate and gate oxide and extend from the top of the gate to the surface of the substrate. Raised source/drain extensions are placed on the surface of a substrate, which extend from the first dielectric spacers to the isolation trenches. Thicker second dielectric spacers are placed adjacent to the first dielectric spacers and extend from the top of the first dielectric spacers to the raised source/drain extensions. Raised source/drain regions are placed on the raised source/drain extensions, and extend from the isolation trenches to the second dielectric spacers. The semiconductor device has very shallow source drain extensions which result in a reduced short channel effect.

Abstract translation: 改进的半导体器件，例如在衬底上具有升高的源极/漏极延伸的MOSFET，其具有蚀刻到衬底的表面中的隔离沟槽。 该器件在栅极和栅极氧化物一侧具有薄的第一介电间隔物，并从栅极的顶部延伸到衬底的表面。 引出的源极/漏极延伸部被放置在从第一电介质间隔物延伸到隔离沟槽的衬底的表面上。 更厚的第二电介质间隔物被放置成与第一电介质间隔物相邻并且从第一介电间隔物的顶部延伸到升高的源极/漏极延伸部分。 升高的源极/漏极区域放置在凸起的源极/漏极延伸部上，并且从隔离沟槽延伸到第二电介质间隔物。 半导体器件具有非常浅的源极漏极延伸，导致短沟道效应降低。

公开(公告)号：US06399450B1

公开(公告)日：2002-06-04

申请号：US09609613

申请日：2000-07-05

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66628 ,  H01L21/28525 ,  H01L29/7834

Abstract: A method of manufacturing an integrated circuit utilizes solid phase epitaxy to form an elevated source and an elevated drain region. The method includes providing an amorphous semiconductor material, doping the amorphous material at a source location and drain location and crystallizing the amorphous semiconductor material via solid phase epitaxy. The semiconductor material can be silicided. A shallow source drain implant can also be provided.

Abstract translation: 制造集成电路的方法利用固相外延形成升高的源极和升高的漏极区域。 该方法包括提供非晶半导体材料，在源极位置和漏极位置掺杂非晶态材料，并通过固相外延结晶非晶半导体材料。 半导体材料可以被硅化。 还可以提供浅源极漏极植入物。