公开(公告)号：US07238983B2

公开(公告)日：2007-07-03

申请号：US11321982

申请日：2005-12-28

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L29/788

CPC classification number: H01L29/66825 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7881

Abstract: In a nonvolatile memory, the select gates (144S) are formed from one conductive layer (e.g. polysilicon or polyside), and the wordlines (144) interconnecting the select gates are made from a different conductive layer (e.g. metal). The wordlines overlie an interlevel dielectric (310) formed over control gates (134). The dielectric thickness can be controlled to reduce the capacitance between the wordlines and the control gates. In some embodiments, the floating gates (120) are fabricated in a self-aligned manner using an isotropic etch of the floating gate layer.

公开(公告)号：US07238575B2

公开(公告)日：2007-07-03

申请号：US10798475

申请日：2004-03-10

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/8239

CPC classification number: H01L29/66825 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7881

Abstract: In a nonvolatile memory, the select gates (144S) are formed from one conductive layer (e.g. polysilicon or polyside), and the wordlines (144) interconnecting the select gates are made from a different conductive layer (e.g. metal). The wordlines overlie an interlevel dielectric (310) formed over control gates (134). The dielectric thickness can be controlled to reduce the capacitance between the wordlines and the control gates. In some embodiments, the floating gates (120) are fabricated in a self-aligned manner using an isotropic etch of the floating gate layer.

Abstract translation: 在非易失性存储器中，选择栅极（144S）由一个导电层（例如多晶硅或多边形）形成，并且互连选择栅极的字线（144）由不同的导电层（例如金属）制成。 字线覆盖在控制栅极（134）上形成的层间电介质（310）。 可以控制电介质厚度以减小字线和控制门之间的电容。 在一些实施例中，使用浮动栅极层的各向同性蚀刻，以自对准的方式制造浮置栅极（120）。

公开(公告)号：US20070093014A1

公开(公告)日：2007-04-26

申请号：US11258115

申请日：2005-10-26

Applicant: Chia-Shun Hsiao ,  Ming-Sheng Tung ,  Hong-Ming Chen ,  Ching-Hsien Huang

Inventor： Chia-Shun Hsiao ,  Ming-Sheng Tung ,  Hong-Ming Chen ,  Ching-Hsien Huang

IPC: H01L21/8234 ,  H01L21/8238

CPC classification number: H01L27/105 ,  H01L21/823456 ,  H01L27/1052

Abstract: The present invention provides a method for preventing doped boron in a dielectric layer from diffusing into a substrate. First, at least one gate is formed on a periphery circuit area and a memory array area of a substrate, respectively, wherein the pattern density in the memory array area is higher than that in the periphery circuit area. Then, a barrier layer is formed on the memory array area and the periphery circuit area, and an undoped oxide barrier is formed on the periphery circuit area. Finally, a silicate glass containing boron is deposited on the memory array area and the periphery circuit area.

Abstract translation: 本发明提供一种防止介电层中的掺杂硼扩散到衬底中的方法。 首先，分别在基板的外围电路区域和存储器阵列区域上形成至少一个栅极，其中存储器阵列区域中的图案密度高于外围电路区域中的图案密度。 然后，在存储器阵列区域和外围电路区域上形成阻挡层，并且在外围电路区域上形成未掺杂的氧化物屏障。 最后，将含硼的硅酸盐玻璃沉积在存储器阵列区域和外围电路区域上。

公开(公告)号：US20070090493A1

公开(公告)日：2007-04-26

申请号：US11248705

申请日：2005-10-11

Applicant: Zhong Dong ,  Chiliang Chen ,  Chung Leung

Inventor： Zhong Dong ,  Chiliang Chen ,  Chung Leung

IPC: H01L23/58 ,  H01L21/318

CPC classification number: H01L21/3144 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/3145

Abstract: Silicon oxide (210) is grown on a silicon region (130). At least a portion (210N) of the silicon oxide (210) adjacent to the silicon region (130) is nitrided. Then some of the silicon oxide (210) is removed, leaving the nitrided portion (210N). Additional silicon oxide is thermally grown on the silicon region (130) under the nitrided silicon oxide portion (210N). This additional silicon oxide and the nitrided portion (210N) form a silicon oxide layer (140) having a high nitrogen concentration adjacent to a surface opposite from the silicon region (130) and a low nitrogen concentration elsewhere. Another nitridation step increases the nitrogen concentration in the silicon oxide layer (140) adjacent to the silicon region, providing a double peak nitrogen profile.

Abstract translation: 氧化硅（210）在硅区（130）上生长。 与硅区域（130）相邻的氧化硅（210）的至少一部分（210 N）被氮化。 然后去除一些氧化硅（210），留下氮化部分（210N）。 另外的氧化硅在氮化硅氧化物部分（210N）下在硅区域（130）上热生长。 该另外的氧化硅和氮化部分（210 N）形成具有与氮区域相反的表面附近的高氮浓度的氧化硅层（140），而在其他地方具有低的氮浓度。 另一个氮化步骤增加邻近硅区域的氧化硅层（140）中的氮浓度，提供双峰氮分布。

公开(公告)号：US07208789B2

公开(公告)日：2007-04-24

申请号：US11062563

申请日：2005-02-23

Applicant: Ting-Shing Wang

Inventor： Ting-Shing Wang

IPC: H01L29/78

CPC classification number: H01L27/10888 ,  H01L27/10832 ,  H01L27/10861 ,  H01L29/945

Abstract: A memory device that includes a semiconductor substrate, and an array of memory cells, each cell being electrically isolated from adjacent cells and including an island formed from the substrate, the island having a top portion and at least one sidewall portion, and being spaced apart from other islands by a bottom surface on the substrate, a capacitor formed contiguous with the sidewall portion, and a transistor formed on the top portion of the island, the transistor including a gate oxide layer formed on a surface of the top portion, a gate formed on the gate oxide layer, and a first and a second diffused regions formed in the top portion, the first diffused region being spaced apart from the second diffused region.

Abstract translation: 一种存储器件，包括半导体衬底和存储器单元阵列，每个单元与相邻单元电隔离并且包括由衬底形成的岛，所述岛具有顶部部分和至少一个侧壁部分，并且间隔开 通过基板上的底面从其他岛形成与该侧壁部分相邻的电容器，以及形成在该岛的顶部的晶体管，该晶体管包括形成于顶部表面的栅极氧化层，栅极 形成在栅极氧化物层上，以及形成在顶部的第一和第二扩散区域，第一扩散区域与第二扩散区域间隔开。

公开(公告)号：US20070075358A1

公开(公告)日：2007-04-05

申请号：US11288194

申请日：2005-11-29

Applicant: Jason Chen ,  Chien Kang Kao

Inventor： Jason Chen ,  Chien Kang Kao

IPC: H01L29/792

CPC classification number: H01L29/7923 ,  H01L29/40117 ,  H01L29/4234

Abstract: A flash memory structure comprises a silicon substrate having at least one concave structure, two doped regions positioned in the semiconductor substrate and at two sides of the concave structure, at least one carrier trapping region positioned in the concave structure, and a conductive layer positioned above the concave structure. The concave structure comprises two grooves having a U-shaped or V-shaped profile. The grooves have an inclined plane with (111) orientation and a bottom plane with (100) orientation of the silicon substrate. The carrier trapping region comprises a dielectric stack positioned in the concave structure, wherein the dielectric stack comprises a first oxide layer positioned on the surface of the silicon substrate, a nitride block positioned on the surface of the first oxide layer and in the concave structure, and a second oxide layer covering the first oxide layer and the nitride block.

Abstract translation: 闪速存储器结构包括具有至少一个凹结构的硅衬底，位于半导体衬底中的两个掺杂区域和位于凹构造两侧的至少一个载体捕获区域，以及位于该凹构造中的导电层 凹形结构。 凹形结构包括具有U形或V形轮廓的两个凹槽。 凹槽具有具有（111）取向的倾斜平面和具有（100）硅衬底取向的底平面。 载体捕获区域包括位于凹形结构中的电介质堆叠，其中电介质叠层包括位于硅衬底表面上的第一氧化物层，位于第一氧化物层的表面上和凹形结构中的氮化物块， 以及覆盖第一氧化物层和氮化物块的第二氧化物层。

公开(公告)号：US20070075353A1

公开(公告)日：2007-04-05

申请号：US11302122

申请日：2005-12-14

Applicant: Jason Chen ,  Chien Kao

Inventor： Jason Chen ,  Chien Kao

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L29/792 ,  B82Y10/00 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/66833 ,  Y10S438/954

Abstract: A flash memory structure comprises a semiconductor substrate having a V-groove, a first doped region positioned in the semiconductor substrate, two second doped regions positioned in the semiconductor substrate and at two sides of the V-groove, a dielectric stack having trapping sites interposed therein positioned on the V-groove, and a conductive layer positioned on the surface of the dielectric stack above the V-groove. A method for forming the V-groove comprises steps of forming a mask layer on the surface of the semiconductor substrate, forming an opening in the mask layer, etching a portion of the semiconductor substrate below the opening to form the V-groove, and removing the mask layer. The semiconductor substrate can be a (100)-oriented silicon substrate, and the V-groove has inclined surface planes with (111) orientation.

公开(公告)号：US20070072388A1

公开(公告)日：2007-03-29

申请号：US11267163

申请日：2005-11-07

Applicant: Chuan-Chi Chen ,  Yang-Yao Su

Inventor： Chuan-Chi Chen ,  Yang-Yao Su

IPC: H01L21/76

CPC classification number: H01L21/76232 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/76237 ,  H01L29/66181

Abstract: Fabrication of a bottle-shaped trench is disclosed. A semiconductor substrate with a trench therein is provided. An ion-doped barrier layer is formed in the trench, exposing the upper portion surfaces of the sidewall of the trench. An ion implantation is performed on the upper portion surfaces of the sidewall of the trench to reduce the oxidation rate in the substrate near the upper portion of the trench. The ion-doped barrier layer is removed, exposing the lower portion and bottom surfaces of the sidewall of the trench. A thermal oxidation treatment is performed, forming an oxide layer on the surface of the trench. The thickness of the oxide layer on the upper portion of the sidewall surface is much thinner than that of the oxide layer on the lower portion of the sidewall surface or that of the bottom surface. A bottle-shaped trench is formed by removing the oxide layer.

Abstract translation: 公开了一种瓶形沟槽的制造。 提供其中具有沟槽的半导体衬底。 在沟槽中形成离子掺杂阻挡层，暴露沟槽侧壁的上部表面。 在沟槽的侧壁的上表面上进行离子注入，以降低在沟槽上部附近的衬底中的氧化速率。 去除离子掺杂阻挡层，暴露沟槽侧壁的下部和底部表面。 进行热氧化处理，在沟槽的表面上形成氧化物层。 侧壁表面的上部的氧化物层的厚度比侧壁表面的下部或底面的氧化物层的厚度薄得多。 通过去除氧化物层形成瓶状沟槽。

公开(公告)号：US07148113B2

公开(公告)日：2006-12-12

申请号：US11160983

申请日：2005-07-19

Applicant: Yu-Piao Wang

Inventor： Yu-Piao Wang

IPC: H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/28044 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/823475 ,  H01L23/5222 ,  H01L29/6653 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating a semiconductor device is described. A gate dielectric layer is formed on a substrate, and several gate structures having a gate conductor, a cap layer and spacers are formed on the gate dielectric layer. A mask layer is formed over the substrate covering a portion of the gate structures. Removing the cap layer and spacers that are not covered by the mask layer. After the mask layer is removed, a dielectric layer is formed over the substrate covering the gate structures. A self-aligned contact hole is formed in the dielectric layer. A conductive layer is formed in the self-aligned contact hole and on the dielectric layer. Since the cap layer and spacers that are not covered by the mask layer are removed and substituted by the dielectric layer having lower dielectric constant property, the parasitic capacitance can be reduced.

Abstract translation: 对半导体装置的制造方法进行说明。 在基板上形成栅极介电层，在栅极电介质层上形成具有栅极导体，盖层和间隔物的多个栅极结构。 在覆盖栅极结构的一部分的衬底上形成掩模层。 去除未被掩模层覆盖的盖层和间隔物。 在去除掩模层之后，在覆盖栅极结构的衬底的上方形成介电层。 在电介质层中形成自对准的接触孔。 在自对准接触孔和电介质层上形成导电层。 由于未被掩模层覆盖的覆盖层和间隔物被具有较低介电常数特性的介电层所取代并替代，所以可以减小寄生电容。

公开(公告)号：US07117059B1

公开(公告)日：2006-10-03

申请号：US11109168

申请日：2005-04-18

Applicant: Hung-Wen Chiou

Inventor： Hung-Wen Chiou

IPC: G06F19/00

CPC classification number: G05B19/41865 ,  Y02P90/20 ,  Y02P90/26

Abstract: A run-to-run control system and a run-to-run controlling method are proposed. The tool process parameters are real-time collected during the semiconductor process is performed and are regarded as the effective factors in the process for providing an optimal operation variables to the tool for the next process run. After modeling the metrology parameters with a set of the tool process parameters with respect to the semiconductor process for its corresponding process run, a set of optimal operation variables is determined by the controller and output to the tool to modify the process recipe of the process. Hence, the process recipe is real-time changed with the process environment to obtain the optimal process performance.

Abstract translation: 提出了运行控制系统和运行控制方法。 在半导体工艺执行过程中实时采集工具工艺参数，并将其视为在下一个工艺运行中为工具提供最佳操作变量的过程中的有效因素。 在使用一组关于半导体工艺的工具过程参数对其相应的过程运行建模测量参数之后，控制器确定一组最佳操作变量，并输出到工具以修改过程的过程配方。 因此，流程配方与流程环境实时更改，以获得最佳过程性能。