公开(公告)号：US20240393983A1

公开(公告)日：2024-11-28

申请号：US18795877

申请日：2024-08-06

Applicant: Micron Technology, Inc.

Inventor： Tony M. Brewer ,  Dean E. Walker

IPC: G06F3/06 ,  G06F9/38

Abstract: System and techniques for host-preferred memory operation are described herein. At a memory-side cache of a memory device that includes accelerator hardware, a first memory operation can be received from a host. A determination that the first memory operation corresponds to a cache set based on an address of the first memory operation is made. A second memory operation can be received from the accelerator hardware. Another determination can be made that the second memory operation corresponds to the cache set. Here, the first memory operation can be enqueued in a host queue of the cache set and the second memory operation can be enqueued in an internal request queue of the cache set. The first memory operation and the second memory operation can be executed as each is dequeued.

公开(公告)号：US20240393978A1

公开(公告)日：2024-11-28

申请号：US18603746

申请日：2024-03-13

Applicant: Micron Technology, Inc.

Inventor： Marco REDAELLI ,  Gianluca COPPOLA

IPC: G06F3/06

Abstract: Implementations described herein relate to memory device background operations. In some implementations, a memory device may receive a background operation command, from a host device, that indicates for the memory device to initiate a background operation for a memory of the memory device. The background operation command may include at least one of an optimization indicator, an idle time indicator, or a power-off time indicator. The memory device may initiate the background operation in accordance with the background operation command.

公开(公告)号：US20240393945A1

公开(公告)日：2024-11-28

申请号：US18670243

申请日：2024-05-21

Applicant: Micron Technology, Inc.

Inventor： Saideep Tiku ,  Poorna Kale

IPC: G06F3/06

Abstract: The subject application relates to in-situ compression of data in a main memory and storing of the compressed data in the same main memory to improve memory optimization. A hardware logic of a memory device may receive modified pages from a first portion of memory array, cause a page compression accelerator in the hardware logic to compress the received modified pages to generate compressed data, and facilitate storing of the compressed data to a second portion of memory array of the same memory device. By using in-situ data compression, memory optimization in a computing device is improved.

公开(公告)号：US12154879B2

公开(公告)日：2024-11-26

申请号：US18231185

申请日：2023-08-07

Applicant: Micron Technology, Inc.

Inventor： Ko Han Lin ,  Tsung Che Tsai

IPC: H01L23/00

Abstract: Improved bump coplanarity for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, when openings in a passivation layer of a semiconductor device are formed to expose surfaces of bond pads, additional openings may also be formed in the passivation layer. The additional openings may have depths shallower than the openings extending to the surfaces of bond pads by leveraging partial exposures to the passivation layer using a leaky chrome process. Subsequently, when active bumps (pillars) are formed on the exposed surfaces of bond pads, dummy bumps (pillars) may be formed on recessed surfaces of the additional openings such that differences in heights above the surface of the passivation between the active bumps and the dummy bumps are reduced to improve coplanarity.

公开(公告)号：US12154853B2

公开(公告)日：2024-11-26

申请号：US18164903

申请日：2023-02-06

Applicant: Micron Technology, Inc.

Inventor： Naveen Kaushik ,  Sidhartha Gupta ,  Pankaj Sharma ,  Haitao Liu

IPC: H01L23/522 ,  G11C5/06 ,  H01L21/48 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27

Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and conductive structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the conductive structures. A sacrificial material is formed over the stack structure and pillar structures are formed to extend vertically through the stack structure and the sacrificial material. The method comprises forming conductive plug structures within upper portions of the pillar structures, forming slots extending vertically through the stack structure and the sacrificial material, at least partially removing the sacrificial material to form openings horizontally interposed between the conductive plug structures, and forming a low-K dielectric material within the openings. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US12154654B2

公开(公告)日：2024-11-26

申请号：US18386518

申请日：2023-11-02

Applicant: Micron Technology, Inc.

Inventor： Erik V. Pohlmann

IPC: G11C7/10 ,  G11C8/18

Abstract: Methods, systems, and devices for dynamic random access memory speed bin compatibility are described. For instance, a device (e.g., a memory device, a host device) may combine a first parameter with a second parameter to generate a third parameter, where the first parameter may be associated with a duration for a clock that is coupled with a memory array to perform a clock cycle and the second parameter may be associated with a timing constraint associated with initiating an access operation for the memory array. The device may determine a latency of a column address strobe based on the third parameter relative to (e.g., satisfying) a threshold value and may access one or more memory cells of the memory array based on the latency of the column address strobe.

公开(公告)号：US12154640B2

公开(公告)日：2024-11-26

申请号：US17856827

申请日：2022-07-01

Applicant: Micron Technology, Inc.

Inventor： Kitae Park

IPC: G11C29/10 ,  G06F3/06 ,  G11C16/16 ,  G11C16/34 ,  G11C29/52

Abstract: Apparatuses, systems, and methods for predetermined pattern program operations are described according to embodiments of the present disclosure. One example method can include determining a portion of a memory device is invalid and performing a predetermined pattern program operation on the portion of the memory device in response to determining the portion of the memory device is invalid.

公开(公告)号：US12153832B2

公开(公告)日：2024-11-26

申请号：US17972364

申请日：2022-10-24

Applicant: Micron Technology, Inc.

Inventor： Elliott C. Cooper-Balis ,  Robert M. Walker ,  Paul Rosenfeld

IPC: G06F3/06

Abstract: An apparatus can include a memory device comprising a memory component and a memory controller that is coupled to the memory component. A memory searching component (MSC) is resident on the apparatus. The MSC can receive an external instruction indicative of performance of an operation to retrieve particular data from the memory component and issue, responsive to receipt of the instruction, a command to the memory controller to cause the memory controller to perform a read request invoking the memory component as part of performance of the operation in the absence of a further external instruction.

公开(公告)号：US12153798B2

公开(公告)日：2024-11-26

申请号：US17866348

申请日：2022-07-15

Applicant: Micron Technology, Inc.

Inventor： Luca Bert

IPC: G06F3/06 ,  G06F13/42

Abstract: A storage product manufactured as a standalone computer component and installed in a computing system to implement an internet application. The storage product includes a network interface, a host interface, computing circuits, and a local storage device having a storage capacity accessible via the network interface. A data generator is connected to the network interface. A local host system is connected to the host interface to control access, made via the network interface. The data generator can send bulk data to the network interface. The computing circuits can generate derived data from the bulk data and store the derived data and/or the bulk data in the local storage device. A central server and/or a user device can connect over internet via to the network interface of the storage product to access the derived data and/or the bulk data.

公开(公告)号：US20240389302A1

公开(公告)日：2024-11-21

申请号：US18658787

申请日：2024-05-08

Applicant: Micron Technology, Inc.

Inventor： Jerome A. Imonigie ,  Chia Ying Lin ,  Davide Dorigo ,  Elisabeth Barr ,  Wan Rou Luo ,  Shi Han Wang ,  Sanjeev Sapra ,  Ashwin Panday ,  Vivek Yadav

IPC: H10B12/00

Abstract: Methods, systems, and devices for contact foot wet pullback with liner wet punch are described. A first etching operation may be performed on a stack of materials and a first insulative material to form a plurality of segments including contacts, the contacts formed from a first conductive material of the stack of materials and extending at least partially through the first insulative material. A first liner material may be deposited over the segments and the first insulative material, and a directional gas bias operation may be performed to transform a portion of the first liner material in contact with an extension of the contacts into a second liner material. A second etching operation may be performed to remove the second liner material and expose a surface of the extension, and a third etching operation may be performed remove at least a portion of the extension.