公开(公告)号：US20130330013A1

公开(公告)日：2013-12-12

申请号：US13963860

申请日：2013-08-09

Applicant: STMicroelectronics International N.V.

Inventor： Surinder Pal SINGH ,  Aneesh BHASIN ,  Kaushik SAHA

IPC: G06T9/00

CPC classification number: G06T9/005 ,  H03M7/40 ,  H04N19/436 ,  H04N19/44 ,  H04N19/46 ,  H04N19/91

Abstract: Parallelization of decoding of a data stream encoded with a variable length code includes determining one or more markers, each of which indicates a position within the encoded data stream. The determined markers are included into the encoded data stream together with the encoded data. At the decoder side, the markers are parsed from the encoded data stream and based on the extracted markers. The encoded data is separated into partitions, which are decoded separately and in parallel.

Abstract translation: 用可变长度码编码的数据流的解码的并行化包括确定一个或多个标记，每个标记表示编码数据流内的位置。 确定的标记与编码数据一起被包括在编码数据流中。 在解码器侧，从编码数据流中解析出标记，并根据提取的标记进行解析。 编码数据被分成分开并且并行解码的分区。

公开(公告)号：US08605530B2

公开(公告)日：2013-12-10

申请号：US13685363

申请日：2012-11-26

Applicant: STMicroelectronics International N.V.

Inventor： Sanjay Kumar Yadav ,  G Penaka Phani ,  Shailendra Sharad

IPC: G11C7/02

CPC classification number: G11C11/24 ,  G11C11/4091 ,  G11C11/4099

Abstract: A memory circuit includes a first memory cell node capacitor, a first memory cell node transistor, a second memory cell node having a second memory cell node capacitor and a second memory cell node transistor, and a pre-charging circuit for pre-charging the first and second memory cell nodes to first and second voltage levels, respectively. The circuit includes a reference memory cell having first and second reference cell transistors with an equalizing transistor between, and a sense amplifier that detects a potential difference between reference bit lines from the reference memory cell and the first or second memory cell node, respectively. The reference cell transistors and equalizing transistor perform a first voltage equalization of the memory cell nodes at a predetermined voltage and a second voltage equalization of the memory cell nodes based on first or second reference signals respectively input to the first or second reference cell transistor.

Abstract translation: 存储电路包括第一存储单元节点电容器，第一存储单元节点晶体管，具有第二存储单元节点电容器和第二存储单元节点晶体管的第二存储单元节点，以及预充电电路， 和第二存储单元节点分别为第一和第二电压电平。 该电路包括参考存储单元，该参考存储单元具有在其之间具有均衡晶体管的第一和第二参考单元晶体管，以及分别检测来自参考存储单元和第一或第二存储单元节点之间的参考位线之间的电位差的读出放大器。 参考单元晶体管和均衡晶体管基于分别输入到第一或第二参考单元晶体管的第一或第二参考信号，以预定电压和存储单元节点的第二电压均衡来执行存储单元节点的第一电压均衡。

公开(公告)号：US08576102B2

公开(公告)日：2013-11-05

申请号：US13310932

申请日：2011-12-05

Applicant: Chandrajit Debnath ,  Pratap Narayan Singh

Inventor： Chandrajit Debnath ,  Pratap Narayan Singh

IPC: H03M1/10

CPC classification number: H03M1/1038 ,  H03M1/46

Abstract: An analog input signal is sampled, and the sampled analog input signal is converted to a digital value. A calibration value is also sampled, and a single bit of an N bit offset value is calculated from the sampled calibration value. The sampling operations are alternatively performed so that one bit of the offset value is generated for each generated digital value. For example, the process is repeated N times to calculate all N bits of the offset value while generating N digital values.

Abstract translation: 对模拟输入信号进行采样，并将采样的模拟输入信号转换为数字值。 还对采样的校准值进行采样，并根据采样的校准值计算N位偏移值的单个位。 替代地执行采样操作，使得针对每个产生的数字值产生偏移值的一个位。 例如，该过程重复N次以计算偏移值的所有N位，同时生成N个数字值。

公开(公告)号：US08552765B2

公开(公告)日：2013-10-08

申请号：US13174078

申请日：2011-06-30

Applicant: Chittoor Parthasarathy ,  Nitin Chawla ,  Kallol Chatterjee ,  Pascal Urard

Inventor： Chittoor Parthasarathy ,  Nitin Chawla ,  Kallol Chatterjee ,  Pascal Urard

IPC: G01R29/02

CPC classification number: H03K3/02 ,  H03K3/0375

Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. We present a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.

Abstract translation: 自适应缩放数字技术试图使系统接近定时故障，以最大限度地提高能量效率。 潜在故障的快速恢复通常是通过减慢系统时钟和/或提供剃须刀解决方案（指令重放）。这些技术会损害吞吐量。 我们提出一种基于动态松弛借贷提供本地原位故障恢复能力的技术。 这种技术是非侵入式的（不需要架构修改），对吞吐量影响最小。

公开(公告)号：US08531227B2

公开(公告)日：2013-09-10

申请号：US12960179

申请日：2010-12-03

Applicant: Vinod Kumar ,  Saiyid Mohammad Irshad Rizvi

Inventor： Vinod Kumar ,  Saiyid Mohammad Irshad Rizvi

IPC: H03L5/00

CPC classification number: H03K19/018528

Abstract: A level shifter includes an output stage transistor and a level controller. The level controller receives a selection signal and provides a reference voltage at a gate terminal of the output stage transistor based on the selection signal. The output stage transistor, on being enabled by the reference voltage, provides a first level shifted output based on a first output reference voltage.

Abstract translation: 电平移位器包括输出级晶体管和电平控制器。 电平控制器接收选择信号，并根据选择信号在输出级晶体管的栅极端提供参考电压。 输出级晶体管在被参考电压使能时，基于第一输出参考电压提供第一电平移位输出。

公开(公告)号：US08526246B2

公开(公告)日：2013-09-03

申请号：US13370035

申请日：2012-02-09

Applicant: Siddharth Gupta ,  Nitin Jain ,  Anand Mishra

Inventor： Siddharth Gupta ,  Nitin Jain ,  Anand Mishra

IPC: G11C7/00

CPC classification number: G11C7/1096 ,  G11C7/18 ,  G11C7/22 ,  G11C8/12 ,  G11C8/18 ,  G11C11/413

Abstract: A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

Abstract translation: 存储器架构包括多个本地输入和输出电路，其中每个本地输入和输出电路与至少一个存储体相关联。 存储器架构还包括全局输入和输出电路，其包括多个全局子写入电路，耦合到多个本地输入和输出电路。一个全局子写入电路被使能，并将写入数据提供给 选择本地输入和输出电路。

公开(公告)号：US08520958B2

公开(公告)日：2013-08-27

申请号：US12702497

申请日：2010-02-09

Applicant: Surinder Pal Singh ,  Aneesh Bhasin ,  Kaushik Saha

Inventor： Surinder Pal Singh ,  Aneesh Bhasin ,  Kaushik Saha

IPC: G06K9/36

CPC classification number: G06T9/005 ,  H03M7/40 ,  H04N19/436 ,  H04N19/44 ,  H04N19/46 ,  H04N19/91

Abstract: Parallelization of decoding of a data stream encoded with a variable length code includes determining one or more markers, each of which indicates a position within the encoded data stream. The determined markers are included into the encoded data stream together with the encoded data. At the decoder side, the markers are parsed from the encoded data stream and based on the extracted markers. The encoded data is separated into partitions, which are decoded separately and in parallel.

公开(公告)号：US08516315B2

公开(公告)日：2013-08-20

申请号：US12906517

申请日：2010-10-18

Applicant: Suraj Prakash

Inventor： Suraj Prakash

IPC: G11C29/00

CPC classification number: G11C29/10 ,  G11C17/00 ,  G11C29/50 ,  G11C2029/0401

Abstract: A method for identifying non stuck-at faults in a read-only memory (ROM) includes generating a golden value of a victim cell, providing a fault-specific pattern through an aggressor cell, generating a test reading of the victim cell in response to the provided fault-specific pattern, and determining whether the ROM has at least one non stuck-at fault. The determination is based on a comparison of the golden value and the test reading of the victim cell.

公开(公告)号：US08489943B2

公开(公告)日：2013-07-16

申请号：US12751111

申请日：2010-03-31

Applicant: Anil K. Dwivedi ,  Akhilesh Chandra ,  Ajay Arun Kulkarni

Inventor： Anil K. Dwivedi ,  Akhilesh Chandra ,  Ajay Arun Kulkarni

IPC: G11C29/00

CPC classification number: G01R31/31715 ,  G11C29/022

Abstract: A system for generating test signals to test characteristics of input-output (IO) cells includes a memory and a processor coupled together through an integrated circuit (IC) chip. The IC chip includes a controller configured to exchange signals between the memory and the processor through IO cells of the IC chip. The IC chip further includes a protocol sequence generator for generating test signals for testing characteristics of the IO cells.

Abstract translation: 用于产生测试信号以测试输入 - 输出（IO）单元的特性的系统包括通过集成电路（IC）芯片耦合在一起的存储器和处理器。 IC芯片包括控制器，配置为通过IC芯片的IO单元在存储器和处理器之间交换信号。 IC芯片还包括协议序列发生器，用于产生用于测试IO单元的特性的测试信号。

公开(公告)号：US08476940B2

公开(公告)日：2013-07-02

申请号：US13310468

申请日：2011-12-02

Applicant: Vinod Kumar

Inventor： Vinod Kumar

IPC: H03B1/00

CPC classification number: H03K3/02 ,  G11C7/1057 ,  G11C7/1069

Abstract: An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors.