公开(公告)号：US11450558B2

公开(公告)日：2022-09-20

申请号：US16992055

申请日：2020-08-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-How Chou ,  Tzu-Hao Fu ,  Tsung-Yin Hsieh ,  Chih-Sheng Chang ,  Shih-Chun Tsai ,  Kun-Chen Ho ,  Yang-Chou Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method for fabricating metal interconnect structure includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer on a substrate; forming a cap layer on the first metal interconnection; forming a second IMD layer on the cap layer; performing a first etching process to remove part of the second IMD layer for forming an opening; performing a plasma treatment process; and performing a second etching process to remove polymers from bottom of the opening.

公开(公告)号：US20220293780A1

公开(公告)日：2022-09-15

申请号：US17827783

申请日：2022-05-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Wen-Jung Liao

IPC: H01L29/778 ,  H01L21/3105 ,  H01L23/31 ,  H01L29/66

Abstract: The present invention provides a method of forming an insulating structure of a high electron mobility transistor (HEMT), firstly, a gallium nitride layer is formed, next, an aluminum gallium nitride layer is formed on the gallium nitride layer, then, a first patterned photoresist layer is formed on the aluminum gallium nitride layer, and a groove is formed in the gallium nitride layer and the aluminum gallium nitride layer, next, an insulating layer is formed and filling up the groove. Afterwards, a second patterned photoresist layer is formed on the insulating layer, wherein the pattern of the first patterned photoresist layer is complementary to the pattern of the second patterned photoresist layer, and part of the insulating layer is removed, then, the second patterned photoresist layer is removed, and an etching step is performed on the remaining insulating layer to remove part of the insulating layer again.

公开(公告)号：US20220293679A1

公开(公告)日：2022-09-15

申请号：US17224140

申请日：2021-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Hsin Hsu ,  Ko-Chi Chen ,  Tzu-Yun Chang ,  Chung-Tse Chen

IPC: H01L27/24 ,  H01L45/00

Abstract: A semiconductor memory device includes a substrate, a dielectric layer on the substrate, and a contact plug in the dielectric layer. An upper portion of the contact plug protrudes from a top surface of the dielectric layer. The upper portion of the contact plug acts as a first electrode. A buffer layer is disposed on the dielectric layer and beside the upper portion of the contact plug. A resistive-switching layer is disposed beside the buffer layer. A second electrode is disposed beside the resistive-switching layer.

公开(公告)号：US11444195B2

公开(公告)日：2022-09-13

申请号：US17118524

申请日：2020-12-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/033 ,  H01L21/324 ,  H01L21/225 ,  H01L21/306 ,  H01L29/10

Abstract: A method of forming a semiconductor structure is disclosed. First, a substrate is provided, including an upper surface. A gate structure is disposed on the upper surface. A spacer is disposed on a sidewall of the gate structure. A first region is located in the substrate. A second region is located in the substrate. The first region and the second region are dry etched to form a first trench and a second trench, respectively. The second region is masked. The first region is then wet etched through the first trench to form a widened first trench. A stress-inducing layer is then formed in the widened first trench and in the second trench.

公开(公告)号：US11444151B2

公开(公告)日：2022-09-13

申请号：US17142268

申请日：2021-01-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Linggang Fang

IPC: H01L49/02 ,  H01L29/94 ,  H01L21/28

Abstract: A poly-insulator-poly (PIP) capacitor including a substrate having a capacitor forming region; a first capacitor dielectric layer on the capacitor forming region; a first poly electrode on the first capacitor dielectric layer; a second capacitor dielectric layer on the first poly electrode; and a second poly electrode on the second capacitor dielectric layer. A third poly electrode is disposed adjacent to a first sidewall of the second poly electrode. A third capacitor dielectric layer is disposed between the third poly electrode and the second poly electrode. A fourth poly electrode is disposed adjacent to a second sidewall of the second poly electrode opposite to the first sidewall. A fourth capacitor dielectric layer is disposed between the fourth poly electrode and the second poly electrode.

公开(公告)号：US20220285500A1

公开(公告)日：2022-09-08

申请号：US17234731

申请日：2021-04-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Hua Chang ,  Jian-Feng Li ,  Hsiang-Chieh Yen

IPC: H01L29/15 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66

Abstract: The present disclosure provides a semiconductor device and a fabricating method thereof, the semiconductor device including a substrate, a nucleation layer, a buffer layer, an active layer and a gate electrode. The nucleation layer is disposed on the substrate, and the buffer layer is disposed on the nucleation layer, wherein the buffer layer includes a first superlattice layer having at least two heteromaterials alternately arranged in a horizontal direction, and a second superlattice layer having at least two heteromaterials vertically stacked along a vertical direction. The at least two heteromaterials stack at least once within the second superlattice layer. The active layer is disposed on the buffer layer, and the gate electrode is disposed on the active layer.

公开(公告)号：US20220285437A1

公开(公告)日：2022-09-08

申请号：US17750386

申请日：2022-05-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Huei Tsai ,  Rai-Min Huang ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H01L27/22 ,  H01L23/528 ,  H01L43/02

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.

公开(公告)号：US20220283217A1

公开(公告)日：2022-09-08

申请号：US17226460

申请日：2021-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ji-Fu KUNG ,  Yi-Lin HUNG ,  Chih-Chung KUO ,  Wei-Che LIN

IPC: G01R31/26

Abstract: An equipment sensing circuit board and an operation method thereof are provided. The equipment sensing circuit board equipped on a semiconductor equipment includes a main sensor, a backup sensor, a first electronic fuse, a second electronic fuse, and a multiplexer. The main sensor and the backup sensor are used to monitor the operation of the semiconductor equipment to output a main sensing signal and a backup sensing signal respectively. The first electronic fuse is disposed on the main sensor to output a first status signal. The second electronic fuse is disposed on the backup sensor to output a second status signal. The multiplexer is connected to the main sensor, the backup sensor, the first electronic fuse and the second electronic fuse. The multiplexer selects to output the main sensing signal or the backup sensing signal according to the combination of the first state signal and the second state signal.

公开(公告)号：US11437436B2

公开(公告)日：2022-09-06

申请号：US17084609

申请日：2020-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

IPC: H01L27/24 ,  H01L45/00

Abstract: A semiconductor device includes a substrate having a memory region and a logic region. A first dielectric layer is disposed on the substrate. A first conductive structure and a second conductive structure are formed in the first dielectric layer and respectively on the memory region and the logic region of the substrate. A memory cell is disposed on the first dielectric layer and directly contacts a top surface of the first conductive structure. A first cap layer is formed on the first dielectric layer and continuously covers a top surface and a sidewall of the memory cell and a top surface of the second conductive structure. A second dielectric layer is formed on the first cap. A third conductive structure is formed in the second dielectric layer and penetrates through the first cap layer to contacts the memory cell.

公开(公告)号：US20220278238A1

公开(公告)日：2022-09-01

申请号：US17747976

申请日：2022-05-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Hsun Shuai ,  Chih-Jung Chen

IPC: H01L29/788 ,  H01L21/28 ,  H01L29/08 ,  H01L21/265 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L29/423

Abstract: A semiconductor memory device includes a substrate having a first active area and a second active area in proximity to the first active area. A trench isolation region is between the first active area and the second active area. A source line region is disposed in the first active area and adjacent to the trench isolation region. An erase gate is disposed on the source line region. A floating gate is disposed on a first side of the erase gate. A first control gate is disposed on the floating gate. A first word line is disposed adjacent to the floating gate and the first control gate and insulated therefrom. A second control gate is disposed on a second side of the erase gate and directly on the trench isolation region. A second word line is disposed adjacent to the second control gate and insulated therefrom.