公开(公告)号：US20220069975A1

公开(公告)日：2022-03-03

申请号：US17409594

申请日：2021-08-23

Applicant: Rambus Inc.

Inventor： Bret G. Stott ,  Craig E. Hampel ,  Frederick A. Ware

IPC: H04L7/033 ,  H04L7/00 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  H03L7/081 ,  H04L1/20

Abstract: A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.

公开(公告)号：US20220066672A1

公开(公告)日：2022-03-03

申请号：US17505503

申请日：2021-10-19

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: G06F3/06

Abstract: A compute system includes an execution unit (e.g. of a CPU) with a memory controller providing access to a hybrid physical memory. The physical memory is “hybrid” in that it combines a cache of relatively fast, durable, and expensive memory (e.g. DRAM) with a larger amount of relatively slow, wear-sensitive, and inexpensive memory (e.g. flash). A hybrid controller component services memory commands from the memory controller component and additionally manages cache fetch and evict operations that keep the cache populated with instructions and data that have a high degree of locality of reference. The memory controller alerts the hybrid controller of available access slots to the cache so that the hybrid controller can use the available access slots for cache fetch and evict operations with minimal interference to the memory controller.

公开(公告)号：US11256613B2

公开(公告)日：2022-02-22

申请号：US16214558

申请日：2018-12-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Craig E. Hampel

IPC: G06F12/00 ,  G06F12/02

Abstract: Improvements are disclosed for “leveling” or averaging out more evenly the number of activate/precharge cycles seen by the rows of a memory component, so that one or more particular rows are not excessively stressed (relative to the other rows). In one embodiment, a memory controller includes remapping facilities arranged to move data stored in a physical row from RPK to RPK′ and modify the mapping from logical row RLK while minimizing impact on normal read/write operations. Remapping operations may be scheduled relative to refresh or other maintenance operations. Remapping operations may be conditionally deferred so as to minimize performance impact.

公开(公告)号：US20210405684A1

公开(公告)日：2021-12-30

申请号：US17368046

申请日：2021-07-06

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F1/08 ,  G06F1/04 ,  G11C7/02 ,  G11C7/04 ,  G11C7/10 ,  G11C7/22

Abstract: The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant.

公开(公告)号：US11211114B2

公开(公告)日：2021-12-28

申请号：US16503189

申请日：2019-07-03

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  John E. Linstadt ,  Thomas J. Giovannini ,  Scott C. Best ,  Kenneth L. Wright

IPC: G11C5/02 ,  G11C11/4093 ,  G11C5/06 ,  G11C11/4076 ,  G11C11/408 ,  G11C29/00 ,  H01L25/065 ,  H01L25/10 ,  G11C11/4096 ,  H01L25/18 ,  G11C7/10 ,  G11C8/12 ,  H01L23/00

Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.

公开(公告)号：US20210397570A1

公开(公告)日：2021-12-23

申请号：US17296532

申请日：2019-11-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Christopher Haywood

IPC: G06F13/16 ,  G06F13/40

Abstract: In a modular memory system, a memory control component, first and second memory sockets and data buffer components are all mounted to the printed circuit board. The first and second memory sockets have electrical contacts to electrically engage counterpart electrical contacts of memory modules to be inserted therein, and each of the data buffer components includes a primary data interface electrically coupled to the memory control component, and first and second secondary data interfaces electrically coupled to subsets of the electrical contacts within the first and second memory sockets, respectively.

公开(公告)号：US20210397554A1

公开(公告)日：2021-12-23

申请号：US17364722

申请日：2021-06-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F12/0802

Abstract: A hybrid memory module includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive flash memory. An address buffer on the module maintains a static, random-access memory (SRAM) cache of addresses for data cached in DRAM.

公开(公告)号：US11204825B2

公开(公告)日：2021-12-21

申请号：US16790637

申请日：2020-02-13

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/52 ,  G06F12/02

Abstract: A memory device is disclosed that includes a row of storage locations that form plural columns. The plural columns include data columns to store data and a tag column to store tag information associated with error locations in the data columns. Each data column is associated with an error correction location including an error code bit location. Logic retrieves and stores the tag information associated with the row in response to activation of the row. A bit error in an accessed data column is repaired by a spare bit location based on the tag information.

公开(公告)号：US11164622B2

公开(公告)日：2021-11-02

申请号：US17101574

申请日：2020-11-23

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/4096 ,  G06F11/10 ,  G11C7/02 ,  G11C29/52 ,  G11C29/04

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

公开(公告)号：US20210280226A1

公开(公告)日：2021-09-09

申请号：US17301089

申请日：2021-03-24

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern

IPC: G11C7/10

Abstract: A memory component includes a memory bank comprising a plurality of storage cells and a data interface block configured to transfer data between the memory component and a component external to the memory component. The memory component further includes a plurality of column interface buses coupled between the memory bank and the data interface block, wherein a first column interface bus of the plurality of column interface buses is configured to transfer data between a first storage cell of the plurality of storage cells and the data interface block during a first access operation and wherein a second column interface bus of the plurality of column interface buses is configured to transfer the data between the first storage cell and the data interface block during a second access operation.