公开(公告)号：US08466720B2

公开(公告)日：2013-06-18

申请号：US13177956

申请日：2011-07-07

Applicant: Nitin Gupta

Inventor： Nitin Gupta

IPC: H03B19/00

CPC classification number: H03K21/023

Abstract: Circuitry and method for dividing the frequency of an input clock signal for use in a prescaler of a digital frequency synthesizer. A flip flop is clocked on a first type of edge of the input clock signal, and provides an output for use as a divided clock signal. Feedback circuitry is clocked on the first type of edge of the input clock signal and provides a signal to a data input of the flip flop based on the inverse of the output of the flip flop.

Abstract translation: 用于划分用于数字频率合成器的预分频器的输入时钟信号的频率的电路和方法。 触发器在输入时钟信号的第一种类型的边沿上被计时，并提供用作分频时钟信号的输出。 反馈电路在输入时钟信号的第一种类型的边缘上被计时，并且基于触发器的输出的反相将信号提供给触发器的数据输入。

公开(公告)号：US08456197B2

公开(公告)日：2013-06-04

申请号：US13118858

申请日：2011-05-31

Applicant: Prashant Dubey ,  Navneet Gupta ,  Shailesh Kumar Pathak ,  Kaushik Saha ,  Gagandeep Singh Sachdev

Inventor： Prashant Dubey ,  Navneet Gupta ,  Shailesh Kumar Pathak ,  Kaushik Saha ,  Gagandeep Singh Sachdev

IPC: G01R19/00 ,  G11C7/00 ,  H03F3/45

CPC classification number: G11C7/065 ,  H04L25/0274

Abstract: A first sensing circuit has input terminals coupled to a true differential signal line and a complementary differential signal line. A second sensing circuit also has input terminals coupled to said true signal and said complementary signal. Each sensing circuit has a true signal sensing path and a complementary signal sensing path. The first sensing circuit has an imbalance that is biased towards the complementary signal sensing path, while the second sensing circuit has an imbalance that is biased towards the true signal sensing path. Outputs from the first and second sensing circuits are processed by a logic circuit producing an output signal that is indicative of whether there a sufficient differential signal for sensing has been developed between the true differential signal line and the complementary differential signal line.

Abstract translation: 第一感测电路具有耦合到真实差分信号线和互补差分信号线的输入端。 第二感测电路还具有耦合到所述真实信号和所述互补信号的输入端子。 每个感测电路具有真实的信号感测路径和互补信号感测路径。 第一感测电路具有偏置于互补信号感测路径的不平衡，而第二感测电路具有被偏置到真实信号感测路径的不平衡。 来自第一和第二感测电路的输出由逻辑电路处理，该逻辑电路产生一个输出信号，该输出信号指示在真实差分信号线和互补差分信号线之间是否存在足够的用于感测的差分信号。

公开(公告)号：US20130044774A1

公开(公告)日：2013-02-21

申请号：US13588137

申请日：2012-08-17

Applicant: Sason Sourani

Inventor： Sason Sourani

IPC: H01S3/10

CPC classification number: H04N9/3129 ,  H04N9/3155 ,  H04N9/3164

Abstract: An intensity of radiation emitted from at least two laser diodes of a projecting apparatus is optimized by providing an offset distance between at least two focal points of the at least two laser diodes and providing a maximum value for radiation intensity emitted by each of the laser diodes, irrespective of simultaneous transmission by one of the laser diodes with another of the laser diodes. The intensity of the radiation emitted from each of the at least two laser diodes is adjusted such that an aggregated value of the radiation intensity emitted by all of the laser diodes within a predefined period of time may exceed a threshold value allowed for the maximum permissible exposure to radiation.

Abstract translation: 通过在至少两个激光二极管的至少两个焦点之间提供偏移距离并且为每个激光二极管发射的辐射强度提供最大值来优化从投影设备的至少两个激光二极管发射的辐射强度 ，而不管其中一个激光二极管与另一个激光二极管同时传输。 调整从至少两个激光二极管中的每一个发射的辐射的强度，使得在预定时间段内由所有激光二极管发射的辐射强度的聚合值可能超过允许最大允许曝光的阈值 到辐射。

公开(公告)号：US08381051B2

公开(公告)日：2013-02-19

申请号：US12821038

申请日：2010-06-22

Applicant: Swapnil Bahl ,  Akhil Garg

Inventor： Swapnil Bahl ,  Akhil Garg

IPC: G01R31/3177 ,  G01R31/40

CPC classification number: G01R31/3177 ,  G01R31/318594

Abstract: A system for testing multi-clock domains in an integrated circuit (IC) includes a plurality of clock sources coupled to a plurality of clock controllers. Each of the clock sources generates a fast clock associated with one of the multi-clock domains. Each of the clock controllers is configured to provide capture pulses to test one clock domain. The capture pulses provided to a clock domain are at a frequency of a fast clock associated with the clock domain. The clock controllers operate sequentially to provide the capture pulses to test the clock domains.

Abstract translation: 用于在集成电路（IC）中测试多时钟域的系统包括耦合到多个时钟控制器的多个时钟源。 每个时钟源产生与多时钟域之一相关联的快速时钟。 每个时钟控制器配置为提供捕获脉冲以测试一个时钟域。 提供给时钟域的捕获脉冲处于与时钟域相关联的快速时钟的频率。 时钟控制器依次操作以提供捕获脉冲来测试时钟域。

公开(公告)号：US08350622B2

公开(公告)日：2013-01-08

申请号：US12622167

申请日：2009-11-19

Applicant: Surendra Kumar ,  Tapas Nandy

Inventor： Surendra Kumar ,  Tapas Nandy

IPC: H03F3/45

CPC classification number: H03F3/45071 ,  H03F1/0266 ,  H03F3/45192 ,  H03F3/45632 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2203/45302 ,  H03F2203/45354 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45434 ,  H03F2203/45446 ,  H03F2203/45702

Abstract: A circuit includes a differential amplifier having a folded cascode architecture with a pair of cascode transistors. A sensing circuit senses a common mode input voltage of a differential input signal applied to the differential amplifier. A bias generator circuit generates a bias voltage for application to the pair of cascode transistors in the folded cascode architecture. The bias generator circuit is connected to an output of the sensing circuit such that the generated bias voltage has a value which is dependent on the sensed common mode input voltage. This dependence stabilizes a common mode output voltage from the differential amplifier in response to changes in the common mode input voltage.

公开(公告)号：US08320209B2

公开(公告)日：2012-11-27

申请号：US12857172

申请日：2010-08-16

Applicant: Sanjay Kumar Yadav ,  G Penaka Phani ,  Shallendra Sharad

Inventor： Sanjay Kumar Yadav ,  G Penaka Phani ,  Shallendra Sharad

IPC: G11C7/02

CPC classification number: G11C11/24 ,  G11C11/4091 ,  G11C11/4099

Abstract: A memory circuit includes a first memory cell node capacitor, a first memory cell node transistor, a second memory cell node having a second memory cell node capacitor and a second memory cell node transistor, and a pre-charging circuit for pre-charging the first and second memory cell nodes to first and second voltage levels, respectively. The circuit includes a reference memory cell having first and second reference cell transistors with an equalizing transistor between, and a sense amplifier that detects a potential difference between reference bit lines from the reference memory cell and the first or second memory cell node, respectively. The reference cell transistors and equalizing transistor perform a first voltage equalization of the memory cell nodes at a predetermined voltage and a second voltage equalization of the memory cell nodes based on first or second reference signals respectively input to the first or second reference cell transistor.

Abstract translation: 存储电路包括第一存储单元节点电容器，第一存储单元节点晶体管，具有第二存储单元节点电容器和第二存储单元节点晶体管的第二存储单元节点，以及预充电电路， 和第二存储单元节点分别为第一和第二电压电平。 该电路包括参考存储单元，该参考存储单元具有在其之间具有均衡晶体管的第一和第二参考单元晶体管，以及分别检测来自参考存储单元和第一或第二存储单元节点之间的参考位线之间的电位差的读出放大器。 参考单元晶体管和均衡晶体管基于分别输入到第一或第二参考单元晶体管的第一或第二参考信号，以预定电压和存储单元节点的第二电压均衡来执行存储单元节点的第一电压均衡。

公开(公告)号：US08269545B2

公开(公告)日：2012-09-18

申请号：US13285541

申请日：2011-10-31

Applicant: Nitin Chawla ,  Chittoor Parthasarathy ,  Kallol Chatterjee ,  Promod Kumar

Inventor： Nitin Chawla ,  Chittoor Parthasarathy ,  Kallol Chatterjee ,  Promod Kumar

IPC: H03H11/26

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A system on chip (SoC) has a digital domain. An adaptive voltage/frequency scaling circuit includes a critical path replica circuit with respect to that digital domain. The critical path replica circuit generates a margin signal, and the adaptive voltage scaling circuit responds to the margin signal by decreasing bias voltage (and/or increasing clock frequency) applied to the digital domain of the system on chip so as to recover available margin. A fail-safe timing sensor is included within the digital domain of the system on chip. The timing sensor generates a flag signal when timing criteria within the digital domain are violated. The adaptive voltage scaling circuit responds to the flag signal by increasing the bias voltage (and/or decreasing the clock frequency) applied to the digital domain of the system on chip so as to implement a recovery operation.

公开(公告)号：US08259486B2

公开(公告)日：2012-09-04

申请号：US12571170

申请日：2009-09-30

Applicant: Ashish Kumar ,  Naveen Batra

Inventor： Ashish Kumar ,  Naveen Batra

IPC: G11C11/00

CPC classification number: G11C11/413 ,  G11C5/145

Abstract: A write boost circuit provides an automatic mode control for boost with different modalities with respect to the external supply voltage and also with respect to the extent of boost required at different process corners. The write boost circuit also takes care of the minimum boost provided to process corners with good writability where less boost is required. The boost is realized in terms of ground raising in the particular context and in general applicable to all other methods.

Abstract translation: 写升压电路提供了一种自动模式控制，用于相对于外部电源电压的不同模式的升压，以及相对于不同工艺角所需的升压程度。 写升压电路还负责处理拐角的最小提升，具有良好的写入性，需要较少的增压。 在特定情况下，通过地面提升实现提升，一般适用于所有其他方法。

公开(公告)号：US08207754B2

公开(公告)日：2012-06-26

申请号：US12391944

申请日：2009-02-24

Applicant: Paras Garg ,  Saiyid Mohammad Irshad Rizvi

Inventor： Paras Garg ,  Saiyid Mohammad Irshad Rizvi

IPC: H03K19/0175

CPC classification number: H03K19/017509

Abstract: An IO buffer module optimized for a wide range of drive levels both in terms of area and performance that includes an IO cell module and at least one IO adder module operatively coupled to said IO cell module for enabling the IO buffer module for the wide range of drive levels. The IO adder module can be added with the IO cell module in a number of different combinations for providing the wide range of drive levels, and the IO buffer module can provide drive solutions from 1 mA to 10 mA or higher, in steps of 0.5 mA drive level.

Abstract translation: IO面板和性能方面针对广泛的驱动器级别进行了优化的IO缓冲器模块，包括IO单元模块和至少一个IO加法器模块，可操作地耦合到所述IO单元模块，以使IO缓冲模块能够在宽范围 驱动级别。 IO加法器模块可以以多种不同的组合添加IO单元模块，以提供宽范围的驱动电平，并且IO缓冲模块可以提供从1 mA到10 mA或更高的驱动解决方案，步长为0.5 mA 驱动级别。

公开(公告)号：US08185338B2

公开(公告)日：2012-05-22

申请号：US12344060

申请日：2008-12-24

Applicant: Rahul Hakoo ,  Chilakala Ravi Kumar ,  Deepak Baranwal

Inventor： Rahul Hakoo ,  Chilakala Ravi Kumar ,  Deepak Baranwal

IPC: G01R31/27 ,  G01R31/02 ,  G01R31/316 ,  G01R31/317

CPC classification number: G01R31/318572

Abstract: A low pin interface module is provided for testing an integrated circuit. The interface module includes an input-output module, a controlling module, a processing module and a storage module specific to the integrated circuit to be tested. The interface module reduces the required number of hardware pins in the integrated circuit for a standalone testing without limiting the integrated circuit testing features. A methodology and a control mechanism achieved with the interface module can be used for the standalone testing of any integrated circuit without using a Joint European Test Action Group test logic interface JTAG implemented following the IEEE Standard 1149.1-1990. The interface module is not limited by a particular debugging platform and allows access to all test features in the integrated circuit with a reduced number of hardware pins and thereby leading to enhanced testing speeds on a tester in parallel and a shorter time-to-a market cycle and a lower development cost.

Abstract translation: 提供了一个低引脚接口模块，用于测试集成电路。 接口模块包括输入输出模块，控制模块，处理模块和专用于要测试的集成电路的存储模块。 接口模块减少了集成电路中所需数量的硬件引脚，用于独立测试，而不会限制集成电路测试功能。 使用接口模块实现的方法和控制机制可用于任何集成电路的独立测试，而不使用符合IEEE标准1149.1-1990的联合欧洲测试行动组测试逻辑接口JTAG。 接口模块不受特定的调试平台的限制，并允许以更少数量的硬件引脚访问集成电路中的所有测试功能，从而导致测试仪并行和更短的市场更短的测试速度 循环和较低的开发成本。