公开(公告)号：US20150042301A1

公开(公告)日：2015-02-12

申请号：US13962958

申请日：2013-08-09

Applicant: STMicroelectronics International N.V.

Inventor： Rajesh NARWAL

IPC: G05F3/08 ,  G05F1/46

CPC classification number: G05F3/08 ,  G05F1/46 ,  G05F1/462 ,  G05F1/468 ,  G05F1/56 ,  G05F1/565 ,  H02M2001/0025

Abstract: An embodiment of an arrangement includes a voltage regulator configured to provide an output voltage, said voltage regulator configured to receive one of a plurality of different regulator reference voltages and a controller configured to provide a selection signal, said selection signal being used to control which of said regulator reference voltages said voltage regulator receives.

Abstract translation: 布置的实施例包括被配置为提供输出电压的电压调节器，所述电压调节器被配置为接收多个不同调节器参考电压中的一个，以及被配置为提供选择信号的控制器，所述选择信号用于控制 所述稳压器所述电压调节器的参考电压接收。

公开(公告)号：US20150028930A1

公开(公告)日：2015-01-29

申请号：US14337896

申请日：2014-07-22

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Stéphane Le Tual ,  Pratap Narayan Singh

IPC: H03H11/26

CPC classification number: H03K5/134 ,  H03K5/13 ,  H03K2005/00032 ,  H03K2005/00208 ,  H03K2005/00215 ,  H03K2217/0018

Abstract: A delay circuit includes first and second transistors and a biasing circuit. The first transistor has a control node coupled to an input node of the delay circuit, a first main current node coupled to a first supply voltage, and a second main current node coupled to an output node of the delay circuit. A second transistor has a control node coupled to the input node, a first main current node coupled to a second supply voltage, and a second main current node coupled to the output node. The biasing circuit is configured to generate first and second differential control voltages , to apply the first differential control voltage to a further control node of the first transistor and to apply the second differential control voltage to a further control node of the second transistor.

Abstract translation: 延迟电路包括第一和第二晶体管和偏置电路。 第一晶体管具有耦合到延迟电路的输入节点的控制节点，耦合到第一电源电压的第一主电流节点和耦合到延迟电路的输出节点的第二主电流节点。 第二晶体管具有耦合到输入节点的控制节点，耦合到第二电源电压的第一主电流节点和耦合到输出节点的第二主电流节点。 偏置电路被配置为产生第一和第二差分控制电压，以将第一差分控制电压施加到第一晶体管的另一控制节点，并将第二差分控制电压施加到第二晶体管的另一个控制节点。

公开(公告)号：US08942502B2

公开(公告)日：2015-01-27

申请号：US13963860

申请日：2013-08-09

Applicant: STMicroelectronics International N.V.

Inventor： Surinder Pal Singh ,  Aneesh Bhasin ,  Kaushik Saha

IPC: G06K9/36 ,  G06K9/46 ,  G06T9/00 ,  H03M7/40 ,  H04N19/44 ,  H04N19/436 ,  H04N19/46 ,  H04N19/91

CPC classification number: G06T9/005 ,  H03M7/40 ,  H04N19/436 ,  H04N19/44 ,  H04N19/46 ,  H04N19/91

Abstract: Parallelization of decoding of a data stream encoded with a variable length code includes determining one or more markers, each of which indicates a position within the encoded data stream. The determined markers are included into the encoded data stream together with the encoded data. At the decoder side, the markers are parsed from the encoded data stream and based on the extracted markers. The encoded data is separated into partitions, which are decoded separately and in parallel.

Abstract translation: 用可变长度码编码的数据流的解码的并行化包括确定一个或多个标记，每个标记表示编码数据流内的位置。 所确定的标记与编码数据一起被包括在编码数据流中。 在解码器侧，从编码数据流中解析出标记，并根据提取的标记进行解析。 编码数据被分成分开并且并行解码的分区。

公开(公告)号：US20150002197A1

公开(公告)日：2015-01-01

申请号：US14046041

申请日：2013-10-04

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (CROLLES 2) SAS

Inventor： Kallol CHATTERJEE ,  Nitin AGARWAL ,  Junaid YOUSUF ,  Nitin GUPTA ,  Pierre DAUTRICHE

IPC: H03L7/095

CPC classification number: H03L7/095

Abstract: A variable frequency clock generator. In aspects, a clock generator includes a droop detector circuit configured to monitor a voltage supply to an integrated circuit. If the supply voltage falls below a specific threshold, a droop voltage flag may be set such that a frequency-locked loop is triggered into a droop voltage mode for handling the voltage droop at the supply voltage. In response, a current control signal that is input to an oscillator that generates a system clock signal is reduced by sinking current away from the current control signal to the oscillator. This results in an immediate reduction on the system clock frequency. Such a state remains until the voltage droop has dissipated when the current path is removed for sinking some of the current.

Abstract translation: 变频时钟发生器。 在方面中，时钟发生器包括下垂检测器电路，其被配置为监视对集成电路的电压供应。 如果电源电压低于特定阈值，则可以设置下降电压标志，使得频率锁定环路被触发到用于处理电源电压的电压下降的下降电压模式。 作为响应，通过将电流从电流控制信号吸收到振荡器来减小输入到产生系统时钟信号的振荡器的电流控制信号。 这将立即降低系统时钟频率。 当去除电流路径以吸收一些电流时，这种状态保持直到电压下降消散。

公开(公告)号：US08917123B2

公开(公告)日：2014-12-23

申请号：US13853247

申请日：2013-03-29

Applicant: STMicroelectronics International N.V.

Inventor： Swapnil Bahl ,  Shray Khullar

IPC: H03L7/00 ,  H03K3/012

CPC classification number: H03K3/012 ,  G01R31/318575

Abstract: An integrated circuit includes an N number of functional logic blocks, with N being greater than or equal to two, and clock staggering test circuitry. When the clock staggering test circuitry is in a shift mode, N staggered shift clock signals are generated for respective ones of the N functional logic blocks. Each of the N staggered shift clock signals has a frequency equal to a frequency of an external test clock signal divided by M, where M is greater than or equal to N. The peak power of the integrated circuit is reduced during the shift mode as a result of the staggered shift clock signals.

Abstract translation: 集成电路包括N个功能逻辑块，N个大于或等于2个，以及时钟交错测试电路。 当时钟交错测试电路处于移位模式时，为N个功能逻辑块中的相应的N个功能逻辑块生成N个交错的移位时钟信号。 N个交错移位时钟信号中的每一个具有等于外部测试时钟信号除以M的频率的频率，其中M大于或等于N.在移位模式期间，集成电路的峰值功率被减小，如 交错时钟信号的结果。

公开(公告)号：US20140361915A1

公开(公告)日：2014-12-11

申请号：US14294300

申请日：2014-06-03

Applicant: STMicroelectronics SA ,  STMicroelectronics International N.V.

Inventor： Stéphane LE TUAL ,  Pratap Narayan SINGH

IPC: H03M1/08 ,  H03K3/013

CPC classification number: H03M1/08 ,  G11C27/024 ,  G11C27/026 ,  H03K3/013 ,  H03K19/018528

Abstract: The invention concerns a circuit comprising: a first transistor (202) having a first main current node coupled to a first voltage signal (CNVDD), a control node coupled to a second voltage signal (CPVDD) and a second main current node coupled to an output node (206) of the circuit; a second transistor (204) having a first main current node coupled to a third voltage signal (CPGND), a control node coupled to a fourth voltage signal (CPGND) and a second main current node coupled to said output node of the circuit; and circuitry (210, 212) adapted to generate said first, second, third and fourth voltage signals based on a pair of differential input signals (CP, CN), wherein said first and second voltage signals are both referenced to a first supply voltage (VDD) and wherein said third and fourth voltage signals are both referenced to a second supply voltage (GND).

Abstract translation: 本发明涉及一种电路，包括：具有耦合到第一电压信号（CNVDD）的第一主电流节点的第一晶体管（202），耦合到第二电压信号（CPVDD）的控制节点和耦合到第一电流信号 输出节点（206）; 第二晶体管（204），其具有耦合到第三电压信号（CPGND）的第一主电流节点，耦合到第四电压信号（CPGND）的控制节点和耦合到所述电路的所述输出节点的第二主电流节点; 以及适于基于一对差分输入信号（CP，CN）产生所述第一，第二，第三和第四电压信号的电路（210,212），其中所述第一和第二电压信号都参考第一电源电压 VDD），并且其中所述第三和第四电压信号都参考第二电源电压（GND）。

公开(公告)号：US20140300386A1

公开(公告)日：2014-10-09

申请号：US14231026

申请日：2014-03-31

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Nitin JAIN ,  Nitin GUPTA

IPC: H03K19/0175

CPC classification number: H03K19/017509

Abstract: A level shifting circuit includes a first inverter including a pair of transistors of opposite conductivity type, the first inverter adapted to receive an input signal in a first voltage domain and further including at least one additional transistor driven by a voltage in a second voltage domain. A second inverter is coupled in series with the first inverter and operable to generate an output signal in the second voltage domain. The second inverter includes a pair of transistors of opposite conductivity type, and further includes at least one additional transistor driven by a voltage in the first voltage domain. The additional transistors are operable to approximately equalize the fall times of output signals generated by the first and second inverters.

Abstract translation: 电平移位电路包括第一反相器，其包括具有相反导电类型的一对晶体管，第一反相器适于接收第一电压域中的输入信号，并且还包括由第二电压域中的电压驱动的至少一个附加晶体管。 第二反相器与第一反相器串联耦合并且可操作以在第二电压域中产生输出信号。 第二反相器包括一对相反导电类型的晶体管，并且还包括由第一电压域中的电压驱动的至少一个附加晶体管。 附加晶体管可操作以近似均衡由第一和第二逆变器产生的输出信号的下降时间。

公开(公告)号：US20140292385A1

公开(公告)日：2014-10-02

申请号：US13853247

申请日：2013-03-29

Applicant: STMicroelectronics International N.V.

Inventor： SWAPNIL BAHL ,  Shray Khullar

IPC: H03K3/012

CPC classification number: H03K3/012 ,  G01R31/318575

Abstract: An integrated circuit includes an N number of functional logic blocks, with N being greater than or equal to two, and clock staggering test circuitry. When the clock staggering test circuitry is in a shift mode, N staggered shift clock signals are generated for respective ones of the N functional logic blocks. Each of the N staggered shift clock signals has a frequency equal to a frequency of an external test clock signal divided by M, where M is greater than or equal to N. The peak power of the integrated circuit is reduced during the shift mode as a result of the staggered shift clock signals.

Abstract translation: 集成电路包括N个功能逻辑块，N个大于或等于2个，以及时钟交错测试电路。 当时钟交错测试电路处于移位模式时，为N个功能逻辑块中的相应的N个功能逻辑块生成N个交错的移位时钟信号。 N个交错移位时钟信号中的每一个具有等于外部测试时钟信号除以M的频率的频率，其中M大于或等于N.在移位模式期间，集成电路的峰值功率被减小，如 交错时钟信号的结果。

公开(公告)号：US20140269137A1

公开(公告)日：2014-09-18

申请号：US14289072

申请日：2014-05-28

Applicant: STMicroelectronics International N.V.

Inventor： Vivek ASTHANA

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C11/417

Abstract: A memory bank includes memory cells and an additional cell to determine an operating voltage of the memory bank. The additional cell has an operating margin that is less than a corresponding operating margin of the other memory cells in the memory bank.

Abstract translation: 存储器体包括存储器单元和用于确定存储体的工作电压的附加单元。 附加单元具有小于存储体中其它存储单元的对应操作裕度的操作裕度。

公开(公告)号：US08782480B2

公开(公告)日：2014-07-15

申请号：US14019329

申请日：2013-09-05

Applicant: STMicroelectronics International N.V.

Inventor： Parul Bansal

IPC: G06F11/00

CPC classification number: G01R31/3177 ,  G06F11/3656

Abstract: An on-chip functional debugger includes one or more functional blocks each providing one or more functional outputs. A hierarchical selection tree is formed by one or more selectors having the output of one of the selectors as a final output and individual selector inputs coupled either to a functional output from the functional blocks or to an output of another selector. A selection signal coupled to the select input of each of the selectors to enable a selected one of its output. An output node coupled to the final output. A method of providing on-chip functional debugging is also provided. A desired functional output from one or more available functional outputs is selected and then the selected functional output is coupled to an output node.

Abstract translation: 片上功能调试器包括一个或多个功能块，每个功能块提供一个或多个功能输出。 分层选择树由具有选择器之一的输出的一个或多个选择器形成为最终输出，以及耦合到功能块的功能输出或另一个选择器的输出的单独选择器输入。 选择信号，其耦合到每个选择器的选择输入以使得其输出中的所选择的一个。 耦合到最终输出的输出节点。 还提供了一种提供片上功能调试的方法。 选择来自一个或多个可用功能输出的期望的功能输出，然后所选择的功能输出耦合到输出节点。