公开(公告)号：US08339388B2

公开(公告)日：2012-12-25

申请号：US12094004

申请日：2006-11-17

Applicant: Bertrand Rivet ,  Frédéric Gautier ,  Benoit Peron

Inventor： Bertrand Rivet ,  Frédéric Gautier ,  Benoit Peron

IPC: G06F3/08 ,  G09G5/00

CPC classification number: G09G5/00 ,  G09G2360/16

Abstract: A method and a circuit for controlling a power recovery stage of a plasma display panel including a resonant circuit of at least one inductive element and one capacitive element, wherein the capacitive element is precharged to half a supply voltage of the display panel.

Abstract translation: 一种用于控制包括至少一个感应元件和一个电容元件的谐振电路的等离子体显示面板的功率恢复阶段的方法和电路，其中电容元件被预充电到显示面板的一半电源电压。

公开(公告)号：US08335121B2

公开(公告)日：2012-12-18

申请号：US12829675

申请日：2010-07-02

Applicant: Cyrille Dray ,  Francois Jacquet ,  Sébastien Barasinski

Inventor： Cyrille Dray ,  Francois Jacquet ,  Sébastien Barasinski

IPC: G11C7/02

CPC classification number: G11C11/413

Abstract: A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.

Abstract translation: 提供了一种用于SRAM存储器信息存储的设备和相应的实现方法。 该设备由电源电压供电并且包括组合在基列中的基本单元的阵列，以及至少一个反射镜单元的至少一个反射镜列，其容易模拟基极柱中的单元的行为。 该装置还包括在立柱中的最大限制单元的反射镜列中的仿真装置，用于改变反射镜列的反射镜电源电压的装置和用于复制仿真基色列中的反射镜电源电压的装置。

公开(公告)号：US08331203B2

公开(公告)日：2012-12-11

申请号：US12374792

申请日：2007-07-20

Applicant: Francesco La Rosa

Inventor： Francesco La Rosa

IPC: G04F8/00 ,  G04F10/00 ,  G01R27/26 ,  G11C11/24

CPC classification number: G11C27/005 ,  G04F10/10 ,  G11C27/024

Abstract: An electronic charge retention circuit for time measurement, including: at least a first capacitive element, a first electrode of which is connected to a floating node (F); at least a second capacitive element, a first electrode of which is connected to the floating node, the first capacitive element having a leakage through its dielectric space and the second capacitive element having a capacitance greater than the first; and at least a first transistor having an isolated control terminal connected to the floating node.

Abstract translation: 一种用于时间测量的电子电荷保持电路，包括：至少第一电容元件，其第一电极连接到浮动节点（F）; 至少第二电容元件，其第一电极连接到所述浮动节点，所述第一电容元件通过其电介质空间具有泄漏，所述第二电容元件具有大于所述第一电容的电容; 以及具有连接到所述浮动节点的隔离控制端的至少第一晶体管。

公开(公告)号：US08321691B2

公开(公告)日：2012-11-27

申请号：US11713887

申请日：2007-03-05

Applicant: Fabrice Romain

Inventor： Fabrice Romain

IPC: G06F21/00

CPC classification number: H04L9/005 ,  G06F7/723 ,  G06F7/725 ,  G06F2207/7223 ,  H04L9/003 ,  H04L2209/046

Abstract: A method for masking a digital quantity used by a calculation executed by an electronic circuit and including several iterations, each including at least one operation which is a function of at least one value depending on the digital quantity, the method including at least one first step of displacement of at least one operand of the operation in a storage element selected independently from the value.

Abstract translation: 一种用于屏蔽由电子电路执行的计算所使用的数字量的方法，包括几次迭代，每个迭代包括至少一个与数字量有关的至少一个值的函数，该方法包括至少一个第一步骤 在与该值独立地选择的存储元件中的操作的至少一个操作数的位移。

公开(公告)号：US08320176B2

公开(公告)日：2012-11-27

申请号：US12374795

申请日：2007-07-20

Applicant: Francesco La Rosa

Inventor： Francesco La Rosa

IPC: G11C11/34

CPC classification number: G11C16/22 ,  G04F10/10 ,  G11C16/0441 ,  G11C16/26

Abstract: An electronic charge retention circuit for time measurement, implanted in an array of EEPROM memory cells, each including a selection transistor in series with a floating-gate transistor, the circuit including, on any one row of memory cells: a first subassembly of at least a first cell, the thickness of the dielectric of the tunnel window of the floating-gate transistor of which is less than that of the other cells; a second subassembly of at least a second cell, the drain and source of the floating-gate transistor of which are interconnected; a third subassembly of at least a third cell; and a fourth subassembly of at least a fourth cell, the tunnel window of which is omitted, the respective floating gates of the transistors of the cells of the four subassemblies being interconnected.

Abstract translation: 一种用于时间测量的电子电荷保持电路，其被注入到EEPROM存储单元的阵列中，每个EEPROM阵列包括与浮栅晶体管串联的选择晶体管，所述电路包括在任何一行存储器单元上：至少第一子组件 第一单元，其浮栅晶体管的隧道窗的电介质的厚度小于其它单元的电介质的厚度; 至少第二单元的第二子组件，其浮置晶体管的漏极和源极相互连接; 至少第三单元的第三子组件; 以及至少第四单元的第四子组件，其通道窗口被省略，四个子组件的单元的晶体管的相应浮动栅互连。

公开(公告)号：US20120225326A1

公开(公告)日：2012-09-06

申请号：US13406749

申请日：2012-02-28

Applicant: Richard Fournel ,  Aomar Halimaoui

Inventor： Richard Fournel ,  Aomar Halimaoui

IPC: H01M8/16 ,  B05D5/12 ,  H01M8/00

CPC classification number: H01M8/16 ,  H01M8/1097 ,  Y02E60/527 ,  Y02P70/56

Abstract: A module of a biofuel cell includes three module elements each having a porous membrane. At least two of the porous membranes are electrically conducting and form the cathode and the anode of the biofuel cell. The third membrane, which is preferably positioned between the two electrically conducting membranes need not be conducting, but defines two emergent cavities within the module. A porous through-channel extends through a silicon support of the module so as to connect one of the emergent cavities to at least one external wall of the silicon support.

Abstract translation: 生物燃料电池的模块包括具有多孔膜的三个模块元件。 至少两个多孔膜是导电的并且形成生物燃料电池的阴极和阳极。 优选地位于两个导电膜之间的第三膜不需要导电，而是限定模块内的两个出射腔。 多孔通道延伸穿过模块的硅支撑件，以便将一个出射空腔连接到硅支撑体的至少一个外壁。

公开(公告)号：US08253090B2

公开(公告)日：2012-08-28

申请号：US12273164

申请日：2008-11-18

Applicant: Frédéric Barbier ,  Benoît Deschamps

Inventor： Frédéric Barbier ,  Benoît Deschamps

IPC: H01L27/00

CPC classification number: H04N5/335 ,  H04N5/2355

Abstract: A method of reading voltages from an image sensor having an array of pixels, each pixel having at least one photodiode connectable to a storage node, the method having: controlling each pixel in a row of pixels to transfer charge accumulated in the photodiode above a first threshold to the storage node at the start and end of a first integration period and reading a first voltage at the storage node of each pixel in the row at the end of the first integration period; controlling of the pixels in the row to transfer charge accumulated in the photodiode above a second threshold to the storage node at the start and end of a second integration period longer than the first integration period, and reading a second voltage value at the storage node of each pixel in the row at the end of the second integration period; controlling each pixel in a row of pixels to transfer charge accumulated in the photodiode to the storage node at the end of a third integration period longer than the first and second integration periods; comparing for each pixel in the row, the first voltage values with a reference voltage; and based on the comparison, for each pixel in the row, performing one of: determining a pixel output value based on the first and/or second voltage values; and reading a third voltage value at the end of the third integration period, and determining a pixel output value based on the second and/or third voltage values.

Abstract translation: 一种从具有像素阵列的图像传感器读取电压的方法，每个像素具有可连接到存储节点的至少一个光电二极管，该方法具有：控制一行像素中的每个像素，以将在光电二极管中累积的电荷传输到第一 在第一积分周期的开始和结束时向存储节点提供阈值，并在第一积分周期结束时读取行中每个像素的存储节点处的第一电压; 控制该行中的像素以在比第一积分周期长的第二积分周期的开始和结束时将累积在光电二极管中的电荷传输到第二阈值到存储节点，并且在存储节点的存储节点处读取第二电压值 在第二积分期间结束的行中的每个像素; 控制一行像素中的每个像素，以在比第一和第二积分周期长的第三积分周期结束时将累积在光电二极管中的电荷传送到存储节点; 比较该行中的每个像素，具有参考电压的第一电压值; 并且基于所述比较，对于所述行中的每个像素，执行以下之一：基于所述第一和/或第二电压值确定像素输出值; 以及在第三积分周期结束时读取第三电压值，以及基于第二和/或第三电压值确定像素输出值。

公开(公告)号：US08203416B2

公开(公告)日：2012-06-19

申请号：US12124940

申请日：2008-05-21

Applicant: Hilal Ezzeddine

Inventor： Hilal Ezzeddine

IPC: H01F5/00 ,  H01F27/29 ,  H01F27/28 ,  H03H5/00

CPC classification number: H01F17/0013 ,  H01F2017/0046 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01P5/10 ,  H01L2924/00

Abstract: A spiral structure having at least one planar winding in at least one first conductive level to form at least one inductive element, wherein the winding is surrounded with a conductive plane and at least one track is formed in a second conductive level and has two ends connected by conductive vias to the plane of the first level, at diametrically opposite positions with respect to the center of the winding.

Abstract translation: 螺旋结构，其具有在至少一个第一导电水平面中的至少一个平面绕组，以形成至少一个电感元件，其中所述绕组被导电平面围绕，并且至少一个轨道形成在第二导电水平上，并且两端连接 通过导电通孔到第一级的平面，在相对于绕组的中心的径向相对的位置。

公开(公告)号：US20120139771A1

公开(公告)日：2012-06-07

申请号：US13166117

申请日：2011-06-22

Applicant: Stéphane Le Tual ,  Pratap Narayan Singh ,  Oleksiy Zabroda ,  Nicola Vannucci

Inventor： Stéphane Le Tual ,  Pratap Narayan Singh ,  Oleksiy Zabroda ,  Nicola Vannucci

IPC: H03M1/12

CPC classification number: H03M1/468

Abstract: A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second plurality of capacitors to the third supply voltage level at the start of a voltage conversion phase.

Abstract translation: 一种差分逐次逼近模数转换器，包括：比较器; 耦合在对应的多个第一开关和比较器的第一输入之间的第一多个电容器，所述第一电容器中的至少一个被布置为接收差分输入信号的第一分量; 以及耦合在相应的多个第二开关和所述比较器的第二输入之间的第二多个电容器，所述第二电容器中的至少一个布置成接收所述差分输入信号的第二分量，其中所述第一和第二多个 的开关各自适于独立地将相应的电容器耦合到所选择的一个：第一电源电压电平; 第二电源电压; 和第三电源电压电平; 以及控制电路，其适于在采样阶段期间对差分输入电压进行采样，并且控制第一和第二开关以在电压转换阶段开始时将第一和第二多个电容器的每个电容器耦合到第三电源电压电平。

公开(公告)号：US08193530B2

公开(公告)日：2012-06-05

申请号：US12539542

申请日：2009-08-11

Applicant: Eric Sabouret ,  Laurent Hoareau ,  Yves Salmon

Inventor： Eric Sabouret ,  Laurent Hoareau ,  Yves Salmon

IPC: H01L27/04

CPC classification number: H01L22/34 ,  H01L24/06 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/4943 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/45099

Abstract: An integrated-circuit semiconductor device includes external electrical connection pads on one face and electrical connection vias under said pads. The electrical connection vias are arranged with a defined pitch in a defined direction. Each via is respectively associated with one of a plurality of adjacent zones of the face. These zones extend perpendicularly to the pitch direction. The electrical connection pads are grouped in adjacent pairs. An insulation space is located between the pads of each pair of electrical connection pads. In a direction perpendicular to the pitch direction, the pads in the pair are spaced apart. The pads of each pair of electrical connection pads extend over a pair of adjacent zones and are associated with two adjacent vias.

Abstract translation: 集成电路半导体器件包括在一个面上的外部电连接焊盘和在所述焊盘之下的电连接通孔。 电连接通孔以确定的方向以限定的间距布置。 每个通孔分别与面部的多个相邻区域中的一个相关联。 这些区域垂直于俯仰方向延伸。 电连接垫被分组成相邻的对。 绝缘空间位于每对电连接焊盘的焊盘之间。 在垂直于俯仰方向的方向上，该对中的焊盘间隔开。 每对电连接焊盘的焊盘在一对相邻的区域上延伸并且与两个相邻的通孔相关联。