公开(公告)号：US20110068403A1

公开(公告)日：2011-03-24

申请号：US12956020

申请日：2010-11-30

Applicant: Michael L. Hattendorf ,  Jack Hwang ,  Anand Murthy ,  Andrew N. Westmeyer

Inventor： Michael L. Hattendorf ,  Jack Hwang ,  Anand Murthy ,  Andrew N. Westmeyer

IPC: H01L27/12

CPC classification number: H01L29/66628 ,  H01L21/26506 ,  H01L29/7834 ,  H01L29/7842

Abstract: Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels.

Abstract translation: 本发明的一些实施例包括提供碳掺杂区域和升高的源极/漏极区域以在NMOS晶体管沟道中提供拉伸应力。

公开(公告)号：US20110006344A1

公开(公告)日：2011-01-13

申请号：US12655323

申请日：2009-12-29

Applicant: Anand Murthy ,  Boyan Boyanov ,  Glenn A. Glass ,  Thomas Hoffmann

Inventor： Anand Murthy ,  Boyan Boyanov ,  Glenn A. Glass ,  Thomas Hoffmann

IPC: H01L29/06 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41725 ,  H01L29/6628 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7842 ,  Y10S438/933

Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

公开(公告)号：US20100102356A1

公开(公告)日：2010-04-29

申请号：US12655329

申请日：2009-12-29

Applicant: Anand Murthy ,  Robert S. Chau ,  Tahir Ghani ,  Kaizad R. Mistry

Inventor： Anand Murthy ,  Robert S. Chau ,  Tahir Ghani ,  Kaizad R. Mistry

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7842

Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

Abstract translation: 描述了用于制造改进的PMOS半导体晶体管的工艺。 凹陷被蚀刻成一层外延硅。 源极和漏极膜沉积在凹槽中。 源极和漏极膜由硅和锗的合金制成。 合金外延沉积在硅层上。 合金因此具有与硅层的晶格结构相同结构的晶格。 然而，由于包含锗，合金的晶格具有比硅层的晶格间隔更大的间隔。 较大的间距在源极和漏极膜之间的晶体管的沟道中产生应力。 应力增加晶体管的IDSAT和IDLIN。 可以通过包括碳而不是锗来以类似的方式制造NMOS晶体管，从而产生拉伸应力。

公开(公告)号：US20100038685A1

公开(公告)日：2010-02-18

申请号：US12191814

申请日：2008-08-14

Applicant: Cory Weber ,  Mark Liu ,  Anand Murthy ,  Hemant Deshpande ,  Daniel B. Aubertine

Inventor： Cory Weber ,  Mark Liu ,  Anand Murthy ,  Hemant Deshpande ,  Daniel B. Aubertine

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7847 ,  H01L29/7849

Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.

Abstract translation: 提供了一种设备。 该器件包括形成在半导体衬底上的晶体管，该晶体管具有导通沟道。 该器件包括与半导体衬底上的导电沟道相邻形成的至少一个边缘位错。 该装置还包括在导电通道之上引入的至少一个自由表面和至少一个边缘错位。

公开(公告)号：US20090152601A1

公开(公告)日：2009-06-18

申请号：US12319887

申请日：2009-01-12

Applicant: Michael L. Hattendorf ,  Jack Hwang ,  Anand Murthy ,  Andrew N. Westmeyer

Inventor： Michael L. Hattendorf ,  Jack Hwang ,  Anand Murthy ,  Andrew N. Westmeyer

IPC: H01L29/78

CPC classification number: H01L29/66628 ,  H01L21/26506 ,  H01L29/7834 ,  H01L29/7842

Abstract: Some embodiments of the present invention include providing carbon doped regions and raised source/drain regions to provide tensile stress in NMOS transistor channels.

Abstract translation: 本发明的一些实施例包括提供碳掺杂区域和升高的源极/漏极区域以在NMOS晶体管沟道中提供拉伸应力。

公开(公告)号：US20090065808A1

公开(公告)日：2009-03-12

申请号：US12269829

申请日：2008-11-12

Applicant: Anand Murthy ,  Robert S. Chau ,  Tahir Ghani ,  Kaizad R. Mistry

Inventor： Anand Murthy ,  Robert S. Chau ,  Tahir Ghani ,  Kaizad R. Mistry

IPC: H01L29/778

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7842

Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

Abstract translation: 描述了用于制造改进的PMOS半导体晶体管的工艺。 凹陷被蚀刻成一层外延硅。 源极和漏极膜沉积在凹槽中。 源极和漏极膜由硅和锗的合金制成。 合金外延沉积在硅层上。 合金因此具有与硅层的晶格结构相同结构的晶格。 然而，由于包含锗，合金的晶格具有比硅层的晶格间隔更大的间隔。 较大的间距在源极和漏极膜之间的晶体管的沟道中产生应力。 应力增加晶体管的IDSAT和IDLIN。 可以通过包括碳而不是锗来以类似的方式制造NMOS晶体管，从而产生拉伸应力。

公开(公告)号：US07492017B2

公开(公告)日：2009-02-17

申请号：US11233854

申请日：2005-09-09

Applicant: Anand Murthy ,  Robert S. Chau ,  Tahir Ghani

Inventor： Anand Murthy ,  Robert S. Chau ,  Tahir Ghani

IPC: H01L21/20

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7842

Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

Abstract translation: 描述了用于制造改进的PMOS半导体晶体管的工艺。 凹陷被蚀刻成一层外延硅。 源极和漏极膜沉积在凹槽中。 源极和漏极膜由硅和锗的合金制成。 合金外延沉积在硅层上。 合金因此具有与硅层的晶格结构相同结构的晶格。 然而，由于包含锗，合金的晶格具有比硅层的晶格间隔更大的间隔。 较大的间距在源极和漏极膜之间的晶体管的沟道中产生应力。 应力增加晶体管的IDSAT和IDLIN。 可以通过包括碳而不是锗来以类似的方式制造NMOS晶体管，从而产生拉伸应力。

公开(公告)号：US20080242037A1

公开(公告)日：2008-10-02

申请号：US11729189

申请日：2007-03-28

Applicant: Bernhard Sell ,  Tahir Ghani ,  Anand Murthy ,  Harry Gomez

Inventor： Bernhard Sell ,  Tahir Ghani ,  Anand Murthy ,  Harry Gomez

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/26513 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method of forming a transistor with self-aligned source and drain extensions in close proximity to a gate dielectric layer of the transistor comprises forming a gate stack on a substrate, implanting a dopant into regions of the substrate adjacent to the gate stack, wherein the dopant increases the etch rate of the substrate and defines the location of the source and drain extensions, forming a pair of spacers on laterally opposite sides of the gate stack that are disposed atop the doped regions of the substrate, etching the doped regions of the substrate and portions of the substrate subjacent to the doped regions, wherein an etch rate of the doped regions is higher than an etch rate of the portions of the substrate subjacent to the doped regions, and depositing a silicon-based material in the etched portions of the substrate.

Abstract translation: 一种形成具有在晶体管的栅介质层附近的具有自对准源极和漏极延伸部分的晶体管的方法包括在衬底上形成栅极堆叠，将掺杂剂注入到与栅极堆叠相邻的衬底区域中，其中 掺杂剂增加了衬底的蚀刻速率并且限定了源极和漏极延伸部分的位置，在栅堆叠的横向相对侧上形成一对间隔物，该衬垫设置在衬底的掺杂区域的顶部，蚀刻衬底的掺杂区域 以及所述衬底的与所述掺杂区域相邻的部分，其中所述掺杂区域的蚀刻速率高于所述衬底的与所述掺杂区域相邻的部分的蚀刻速率，以及在所述掺杂区域的蚀刻部分中沉积硅基材料 基质。

公开(公告)号：US20070238236A1

公开(公告)日：2007-10-11

申请号：US11391928

申请日：2006-03-28

Applicant: Ted Cook ,  Bernhard Sell ,  Anand Murthy

Inventor： Ted Cook ,  Bernhard Sell ,  Anand Murthy

IPC: H01L21/8234 ,  H01L21/336

CPC classification number: H01L29/665 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method and apparatus to improve the contact formation of salicide and reduce the external resistance of a transistor is disclosed. A gate electrode is formed on a surface of a substrate. A source region and a drain region are isotropically etched in the substrate. A Silicon Germanium alloy is doped in situ with Boron in the source region and in the drain region. Silicon is deposited on the Silicon Germanium alloy. Nickel is deposited on the Silicon. A Nickel Silicon Germanium silicide layer is formed on the Silicon Germanium alloy. A Nickel Silicon silicide layer is formed on the Nickel Silicon Germanium silicide layer.

Abstract translation: 公开了一种改善硅化物的接触形成并降低晶体管的外部电阻的方法和装置。 在基板的表面上形成栅电极。 源极区域和漏极区域在基板中被各向同性地蚀刻。 在源区和漏区中硼原位掺杂硅锗合金。 硅沉积在硅锗合金上。 镍沉积在硅上。 在硅锗合金上形成硅锗硅化硅层。 镍硅化硅层形成在硅锗硅化硅层上。

公开(公告)号：US20070224766A1

公开(公告)日：2007-09-27

申请号：US11387012

申请日：2006-03-21

Applicant: Willy Rachmady ,  Anand Murthy

Inventor： Willy Rachmady ,  Anand Murthy

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/32134 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method to selectively etch, and hence pattern, a semiconductor film deposited non-selectively is described. In one embodiment, a carbon-doped silicon film is deposited non-selectively such that the film forms an epitaxial region where deposited on a crystalline surface and an amorphous region where deposited on an amorphous surface. A four-component wet etch mixture is tuned to selectively etch the amorphous region while retaining the epitaxial region, wherein the four-component wet etch mixture comprises an oxidizing agent, an etchant, a buffer and a diluent.

Abstract translation: 描述了非选择性地沉积半导体膜并因此图案化的方法。 在一个实施例中，碳掺杂硅膜被非选择性地沉积，使得膜形成沉积在沉积在非晶表面上的结晶表面和非晶区域上的外延区域。 调节四组分湿蚀刻混合物以选择性地蚀刻非晶区域同时保留外延区域，其中四组分湿蚀刻混合物包含氧化剂，蚀刻剂，缓冲剂和稀释剂。