公开(公告)号：US20210202378A1

公开(公告)日：2021-07-01

申请号：US16728887

申请日：2019-12-27

Applicant: Gilbert Dewey ,  Ryan Keech ,  Cory Bomberger ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Willy Rachmady ,  Anand Murthy

Inventor： Gilbert Dewey ,  Ryan Keech ,  Cory Bomberger ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Willy Rachmady ,  Anand Murthy

IPC: H01L23/522 ,  H01L27/12 ,  H01L21/762 ,  H01L21/768

Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

公开(公告)号：US20070224766A1

公开(公告)日：2007-09-27

申请号：US11387012

申请日：2006-03-21

Applicant: Willy Rachmady ,  Anand Murthy

Inventor： Willy Rachmady ,  Anand Murthy

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/32134 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method to selectively etch, and hence pattern, a semiconductor film deposited non-selectively is described. In one embodiment, a carbon-doped silicon film is deposited non-selectively such that the film forms an epitaxial region where deposited on a crystalline surface and an amorphous region where deposited on an amorphous surface. A four-component wet etch mixture is tuned to selectively etch the amorphous region while retaining the epitaxial region, wherein the four-component wet etch mixture comprises an oxidizing agent, an etchant, a buffer and a diluent.

Abstract translation: 描述了非选择性地沉积半导体膜并因此图案化的方法。 在一个实施例中，碳掺杂硅膜被非选择性地沉积，使得膜形成沉积在沉积在非晶表面上的结晶表面和非晶区域上的外延区域。 调节四组分湿蚀刻混合物以选择性地蚀刻非晶区域同时保留外延区域，其中四组分湿蚀刻混合物包含氧化剂，蚀刻剂，缓冲剂和稀释剂。

公开(公告)号：US20210202476A1

公开(公告)日：2021-07-01

申请号：US16728983

申请日：2019-12-27

Applicant: Cheng-Ying Huang ,  Gilbert Dewey ,  Ashish Agrawal ,  Kimin Jun ,  Willy Rachmady ,  Zachary Geiger ,  Cory Bomberger ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy ,  Jack Kavalieros

Inventor： Cheng-Ying Huang ,  Gilbert Dewey ,  Ashish Agrawal ,  Kimin Jun ,  Willy Rachmady ,  Zachary Geiger ,  Cory Bomberger ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy ,  Jack Kavalieros

IPC: H01L27/06 ,  H01L21/683 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/04 ,  H01L29/08 ,  H01L27/092

Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.

公开(公告)号：US07364976B2

公开(公告)日：2008-04-29

申请号：US11387012

申请日：2006-03-21

Applicant: Willy Rachmady ,  Anand Murthy

Inventor： Willy Rachmady ,  Anand Murthy

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/32134 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method to selectively etch, and hence pattern, a semiconductor film deposited non-selectively is described. In one embodiment, a carbon-doped silicon film is deposited non-selectively such that the film forms an epitaxial region where deposited on a crystalline surface and an amorphous region where deposited on an amorphous surface. A four-component wet etch mixture is tuned to selectively etch the amorphous region while retaining the epitaxial region, wherein the four-component wet etch mixture comprises an oxidizing agent, an etchant, a buffer and a diluent.

Abstract translation: 描述了非选择性地沉积半导体膜并因此图案化的方法。 在一个实施例中，碳掺杂硅膜被非选择性地沉积，使得膜形成沉积在沉积在非晶表面上的结晶表面和非晶区域上的外延区域。 调节四组分湿蚀刻混合物以选择性地蚀刻非晶区域同时保留外延区域，其中四组分湿蚀刻混合物包含氧化剂，蚀刻剂，缓冲剂和稀释剂。

公开(公告)号：US07517772B2

公开(公告)日：2009-04-14

申请号：US12034118

申请日：2008-02-20

Applicant: Willy Rachmady ,  Anand Murthy

Inventor： Willy Rachmady ,  Anand Murthy

IPC: H01L21/20

CPC classification number: H01L29/7848 ,  H01L21/32134 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method to selectively etch, and hence pattern, a semiconductor film deposited non-selectively is described. In one embodiment, a carbon-doped silicon film is deposited non-selectively such that the film forms an epitaxial region where deposited on a crystalline surface and an amorphous region where deposited on an amorphous surface. A four-component wet etch mixture is tuned to selectively etch the amorphous region while retaining the epitaxial region, wherein the four-component wet etch mixture comprises an oxidizing agent, an etchant, a buffer and a diluent.

Abstract translation: 描述了非选择性地沉积半导体膜并因此图案化的方法。 在一个实施例中，碳掺杂硅膜被非选择性地沉积，使得膜形成沉积在沉积在非晶表面上的结晶表面和非晶区域上的外延区域。 调节四组分湿蚀刻混合物以选择性地蚀刻非晶区域同时保留外延区域，其中四组分湿蚀刻混合物包含氧化剂，蚀刻剂，缓冲剂和稀释剂。

公开(公告)号：US20080153237A1

公开(公告)日：2008-06-26

申请号：US12034118

申请日：2008-02-20

Applicant: Willy Rachmady ,  Anand Murthy

Inventor： Willy Rachmady ,  Anand Murthy

IPC: H01L21/20 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/32134 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method to selectively etch, and hence pattern, a semiconductor film deposited non-selectively is described. In one embodiment, a carbon-doped silicon film is deposited non-selectively such that the film forms an epitaxial region where deposited on a crystalline surface and an amorphous region where deposited on an amorphous surface. A four-component wet etch mixture is tuned to selectively etch the amorphous region while retaining the epitaxial region, wherein the four-component wet etch mixture comprises an oxidizing agent, an etchant, a buffer and a diluent.

Abstract translation: 描述了非选择性地沉积半导体膜并因此图案化的方法。 在一个实施例中，碳掺杂硅膜被非选择性地沉积，使得膜形成沉积在沉积在非晶表面上的结晶表面和非晶区域上的外延区域。 调节四组分湿蚀刻混合物以选择性地蚀刻非晶区域同时保留外延区域，其中四组分湿蚀刻混合物包含氧化剂，蚀刻剂，缓冲剂和稀释剂。

公开(公告)号：US20070004123A1

公开(公告)日：2007-01-04

申请号：US11173660

申请日：2005-06-30

Applicant: Mark Bohr ,  Steven Keating ,  Thomas Letson ,  Anand Murthy ,  Donald O'Neill ,  Willy Rachmady

Inventor： Mark Bohr ,  Steven Keating ,  Thomas Letson ,  Anand Murthy ,  Donald O'Neill ,  Willy Rachmady

IPC: H01L21/8238

CPC classification number: H01L29/045 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.

Abstract translation: 实施例是改进的晶体管结构和制造该结构的方法。 特别地，实施例的湿蚀刻形成具有改进的尖端形状的源极和漏极区域，以通过改善短沟道效应的控制，增加饱和电流，改善冶金栅极长度的控制，增加载流子迁移率来提高晶体管的性能 并且在源极和漏极与硅化物之间的界面处降低接触电阻。

公开(公告)号：US20130153965A1

公开(公告)日：2013-06-20

申请号：US13764675

申请日：2013-02-11

Applicant: Boyan Boyanov ,  Anand Murthy ,  Brian S. Doyle ,  Robert Chau

Inventor： Boyan Boyanov ,  Anand Murthy ,  Brian S. Doyle ,  Robert Chau

IPC: H01L29/78

CPC classification number: H01L29/7849 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/092 ,  H01L29/78

Abstract: Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.

Abstract translation: 本发明的各种实施例涉及一种CMOS器件，其具有（1）选择性地沉积在渐变硅锗衬底的第一区域上的硅材料的NMOS沟道，使得选择性沉积的硅材料经历由晶格间隔引起的拉伸应变 硅材料小于第一区域处的渐变硅锗衬底材料的晶格间距，以及（2）选择性地沉积在衬底的第二区域上的硅锗材料的PMOS沟道，使得选择性沉积的硅锗材料经历 由选择性沉积的硅锗材料的晶格间距引起的压缩应变大于第二区域处的分级硅锗衬底材料的晶格间距。

公开(公告)号：US08373154B2

公开(公告)日：2013-02-12

申请号：US12609711

申请日：2009-10-30

Applicant: Boyan Boyanov ,  Anand Murthy ,  Brian S. Doyle ,  Robert Chau

Inventor： Boyan Boyanov ,  Anand Murthy ,  Brian S. Doyle ,  Robert Chau

IPC: H01L29/08 ,  H01L31/0312 ,  H01L29/12 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/7849 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/092 ,  H01L29/78

Abstract: Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.

公开(公告)号：US08154087B2

公开(公告)日：2012-04-10

申请号：US13107739

申请日：2011-05-13

Applicant: Ted E. Cook, Jr. ,  Bernhard Sell ,  Anand Murthy

Inventor： Ted E. Cook, Jr. ,  Bernhard Sell ,  Anand Murthy

IPC: H01L27/088

CPC classification number: H01L29/7848 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/7834

Abstract: A multi-component strain-inducing semiconductor region is described. In an embodiment, formation of such a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In one embodiment, the multi-component strain-inducing material region comprises a first portion and a second portion which are separated by an interface. In a specific embodiment, the concentration of charge-carrier dopant impurity atoms of the two portions are different from one another at the interface.

Abstract translation: 描述了多组分应变诱导半导体区域。 在一个实施方案中，在与晶体衬底横向相邻的这种应变诱导半导体区域的形成导致赋予晶体衬底的单轴应变，从而提供应变晶体衬底。 在一个实施例中，多组分应变诱导材料区域包括由界面分离的第一部分和第二部分。 在具体实施方案中，两部分的电荷 - 载流子掺杂剂杂质原子的浓度在界面处彼此不同。