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    Semiconductor device having self-aligned epitaxial source and drain extensions
    1.
    发明申请
    Semiconductor device having self-aligned epitaxial source and drain extensions 有权
    具有自对准外延源极和漏极延伸部分的半导体器件

    公开(公告)号：US20080242037A1

    公开(公告)日：2008-10-02

    申请号：US11729189

    申请日：2007-03-28

    申请人： Bernhard Sell ,  Tahir Ghani ,  Anand Murthy ,  Harry Gomez

    发明人： Bernhard Sell ,  Tahir Ghani ,  Anand Murthy ,  Harry Gomez

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7848 ,  H01L21/26513 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

    摘要： A method of forming a transistor with self-aligned source and drain extensions in close proximity to a gate dielectric layer of the transistor comprises forming a gate stack on a substrate, implanting a dopant into regions of the substrate adjacent to the gate stack, wherein the dopant increases the etch rate of the substrate and defines the location of the source and drain extensions, forming a pair of spacers on laterally opposite sides of the gate stack that are disposed atop the doped regions of the substrate, etching the doped regions of the substrate and portions of the substrate subjacent to the doped regions, wherein an etch rate of the doped regions is higher than an etch rate of the portions of the substrate subjacent to the doped regions, and depositing a silicon-based material in the etched portions of the substrate.

    摘要翻译： 一种形成具有在晶体管的栅介质层附近的具有自对准源极和漏极延伸部分的晶体管的方法包括在衬底上形成栅极堆叠，将掺杂剂注入到与栅极堆叠相邻的衬底区域中，其中 掺杂剂增加了衬底的蚀刻速率并且限定了源极和漏极延伸部分的位置，在栅堆叠的横向相对侧上形成一对间隔物，该衬垫设置在衬底的掺杂区域的顶部，蚀刻衬底的掺杂区域 以及所述衬底的与所述掺杂区域相邻的部分，其中所述掺杂区域的蚀刻速率高于所述衬底的与所述掺杂区域相邻的部分的蚀刻速率，以及在所述掺杂区域的蚀刻部分中沉积硅基材料 基质。

    Semiconductor device having self-aligned epitaxial source and drain extensions
    2.
    发明授权
    Semiconductor device having self-aligned epitaxial source and drain extensions 有权
    具有自对准外延源极和漏极延伸部分的半导体器件

    公开(公告)号：US07732285B2

    公开(公告)日：2010-06-08

    申请号：US11729189

    申请日：2007-03-28

    申请人： Bernhard Sell ,  Tahir Ghani ,  Anand Murthy ,  Harry Gomez

    发明人： Bernhard Sell ,  Tahir Ghani ,  Anand Murthy ,  Harry Gomez

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7848 ,  H01L21/26513 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

    摘要： A method of forming a transistor with self-aligned source and drain extensions in close proximity to a gate dielectric layer of the transistor comprises forming a gate stack on a substrate, implanting a dopant into regions of the substrate adjacent to the gate stack, wherein the dopant increases the etch rate of the substrate and defines the location of the source and drain extensions, forming a pair of spacers on laterally opposite sides of the gate stack that are disposed atop the doped regions of the substrate, etching the doped regions of the substrate and portions of the substrate subjacent to the doped regions, wherein an etch rate of the doped regions is higher than an etch rate of the portions of the substrate subjacent to the doped regions, and depositing a silicon-based material in the etched portions of the substrate.

    摘要翻译： 一种形成具有在晶体管的栅介质层附近的具有自对准源极和漏极延伸部分的晶体管的方法包括在衬底上形成栅极堆叠，将掺杂剂注入到与栅极堆叠相邻的衬底区域中，其中 掺杂剂增加了衬底的蚀刻速率并且限定了源极和漏极延伸部分的位置，在栅堆叠的横向相对侧上形成一对间隔物，该衬垫设置在衬底的掺杂区域的顶部，蚀刻衬底的掺杂区域 以及所述衬底的与所述掺杂区域相邻的部分，其中所述掺杂区域的蚀刻速率高于所述衬底的与所述掺杂区域相邻的部分的蚀刻速率，以及在所述掺杂区域的蚀刻部分中沉积硅基材料 基质。

    MULTI-GATE SEMICONDUCTOR DEVICE WITH SELF-ALIGNED EPITAXIAL SOURCE AND DRAIN
    6.
    发明申请
    MULTI-GATE SEMICONDUCTOR DEVICE WITH SELF-ALIGNED EPITAXIAL SOURCE AND DRAIN 有权
    具有自对准外延源和漏极的多栅极半导体器件

    公开(公告)号：US20110147842A1

    公开(公告)日：2011-06-23

    申请号：US12646518

    申请日：2009-12-23

    申请人： Annalisa Cappellani ,  Tahir Ghani ,  Kuan-Yueh Shen ,  Anand S. Murthy ,  Harry Gomez

    发明人： Annalisa Cappellani ,  Tahir Ghani ,  Kuan-Yueh Shen ,  Anand S. Murthy ,  Harry Gomez

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66545 ,  H01L21/26506 ,  H01L21/3065 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

    摘要： A channel strained multi-gate transistor with low parasitic resistance and method of manufacturing the same. A gate stack may be formed over a semiconductor fin having a gate-coupled sidewall height (Hsi), an etch rate controlling dopant may be implanted into a source/drain region of the semiconductor fin adjacent to the gate stack and into a source/drain extension region of the semiconductor fin. The doped fin region may be etched to remove a thickness of the semiconductor fin equal to at least Hsi proximate a channel region and form a source/drain extension undercut. A material may be grown on the exposed semiconductor substrate to form a regrown source/drain fin region filling the source/drain extension undercut region.

    摘要翻译： 具有低寄生电阻的通道应变多栅极晶体管及其制造方法。 可以在具有栅极耦合侧壁高度（Hsi）的半导体鳍片上形成栅极堆叠，蚀刻速率控制掺杂剂可以注入到与栅极堆叠相邻的半导体鳍片的源极/漏极区域中并且被注入到源极/漏极 半导体鳍片的延伸区域。 可以蚀刻掺杂散热片区域以除去等于沟道区域附近的至少Hsi的半导体鳍片的厚度并形成源极/漏极延伸底切。 可以在暴露的半导体衬底上生长材料以形成填充源极/漏极延伸底切区域的再生长源极/漏极鳍区域。

    Multi-gate semiconductor device with self-aligned epitaxial source and drain
    7.
    发明授权
    Multi-gate semiconductor device with self-aligned epitaxial source and drain 有权
    具有自对准外延源极和漏极的多栅极半导体器件

    公开(公告)号：US08313999B2

    公开(公告)日：2012-11-20

    申请号：US12646518

    申请日：2009-12-23

    申请人： Annalisa Cappellani ,  Tahir Ghani ,  Kuan-Yueh Shen ,  Anand S. Murthy ,  Harry Gomez

    发明人： Annalisa Cappellani ,  Tahir Ghani ,  Kuan-Yueh Shen ,  Anand S. Murthy ,  Harry Gomez

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66545 ,  H01L21/26506 ,  H01L21/3065 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

    摘要： A channel strained multi-gate transistor with low parasitic resistance and method of manufacturing the same. A gate stack may be formed over a semiconductor fin having a gate-coupled sidewall height (Hsi), an etch rate controlling dopant may be implanted into a source/drain region of the semiconductor fin adjacent to the gate stack and into a source/drain extension region of the semiconductor fin. The doped fin region may be etched to remove a thickness of the semiconductor fin equal to at least Hsi proximate a channel region and form a source/drain extension undercut. A material may be grown on the exposed semiconductor substrate to form a regrown source/drain fin region filling the source/drain extension undercut region.

    摘要翻译： 具有低寄生电阻的通道应变多栅极晶体管及其制造方法。 可以在具有栅极耦合侧壁高度（Hsi）的半导体鳍片上形成栅极堆叠，蚀刻速率控制掺杂剂可以注入到与栅极堆叠相邻的半导体鳍片的源极/漏极区域中并且被注入到源极/漏极 半导体鳍片的延伸区域。 可以蚀刻掺杂散热片区域以除去等于沟道区域附近的至少Hsi的半导体鳍片的厚度并形成源极/漏极延伸底切。 可以在暴露的半导体衬底上生长材料以形成填充源极/漏极延伸底切区域的再生长源极/漏极鳍区域。