公开(公告)号：US20060197567A1

公开(公告)日：2006-09-07

申请号：US11360988

申请日：2006-02-23

Applicant: Andreas Jakobs ,  Torsten Hinz ,  Benaissa Zaryouh

Inventor： Andreas Jakobs ,  Torsten Hinz ,  Benaissa Zaryouh

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  H03K5/133 ,  H03K2005/00026 ,  H03L7/0814 ,  H03L7/087

Abstract: The invention relates to a DLL circuit for providing an adjustable time delay of a periodic input signal, said circuit having controllable delay elements which are connected in series and form a delay chain, having a phase detector in order to generate a control signal on the basis of the periodic input signal and a periodic signal which has been delayed by the delay chain, the delay of each of the delay elements being adjusted on the basis of the control signal, and having a selection unit which is respectively connected to one of the delay elements in order to apply an output signal from one of the delay elements to an output of the DLL circuit on the basis of a selection variable which has been provided, and a compensation circuit which modifies the selection signal such that an additional delay (which is caused at least by the selection unit) between the periodic input signal and the output signal from the DLL circuit is compensated for.

Abstract translation: 本发明涉及一种用于提供周期性输入信号的可调时间延迟的DLL电路，所述电路具有可串联连接并形成延迟链的可控延迟元件，具有相位检测器，以便在此基础上产生控制信号 和延迟链延迟的周期信号，基于控制信号调整每个延迟元件的延迟，并且具有选择单元，其分别连接到延迟链中的一个延迟 元件，以便根据所提供的选择变量将来自延迟元件之一的输出信号施加到DLL电路的输出;以及补偿电路，其修改选择信号，使得附加延迟（即 至少由选择单元引起的）周期性输入信号与来自DLL电路的输出信号进行补偿。

公开(公告)号：US20060109869A1

公开(公告)日：2006-05-25

申请号：US11236970

申请日：2005-09-28

Applicant: Andreas Jakobs ,  Eckehard Plaettner

Inventor： Andreas Jakobs ,  Eckehard Plaettner

IPC: H04J3/06

CPC classification number: G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C2207/2254

Abstract: The invention describes a method for adjusting signal propagation times in a memory system in which a controller is connected to at least one memory chip via a plurality of connecting lines for the purpose of transmitting control and data signals and at least one time reference signal. In line with the invention, the propagation time differences between connecting lines are ascertained from the result of echo measurements. To this end a respective transmitted pulse is applied to one end, selected as the transmission end, of the connecting lines in question, while the other end of the connecting lines in question is respectively terminated with a reflective termination. At the transmission end, the echo time which elapses between one edge of the transmitted pulse and the appearance of this edge's echo reflected from the other end is measured. On the basis of the ascertained propagation time differences, regulatable delay devices are set in order to compensate for these propagation time differences. The subject matter of the invention is also circuit arrangements for performing this method.

公开(公告)号：US20060031620A1

公开(公告)日：2006-02-09

申请号：US11174950

申请日：2005-07-05

Applicant: Andreas Jakobs ,  Peter Gregorius

Inventor： Andreas Jakobs ,  Peter Gregorius

IPC: G06F13/14

CPC classification number: G06F13/1678

Abstract: The invention relates to a memory controller for the exchange of data between a digital memory arrangement (RAMs) and a data processing device, comprising a distributor circuit, to be connected to the data processing device, and a plurality m≧2 of parallel transfer blocks, each of which is constructed for transmitting data words which in each case consist of n parallel data bits. According to the invention, in at least one group of p≧2 transfer blocks, only one of the transfer blocks is configured as a master for the transfer of strobe signals by this transfer block. All other transfer blocks of the group are in each case configured as a slave in that the strobe terminals with this transfer block provided for transmitting the strobe signal to the distributor circuit are connected to the strobe terminals of the master which are provided for transmitting the strobe signal to the distributor circuit.

Abstract translation: 本发明涉及一种存储器控制器，用于在数字存储装置（RAM）和数据处理装置之间进行数据交换，数据处理装置包括要连接到数据处理装置的分配器电路和多个m = 2并行转换 块，每个块被构造用于发送在每种情况下由n个并行数据位组成的数据字。 根据本发明，在至少一组p> = 2个传输块中，只有一个传输块被配置为用于由该传输块传送选通信号的主机。 组中的所有其他传送块在每种情况下均被配置为从设备，其中具有用于将选通信号发送到分配器电路的传输块的选通端子连接到主设备用于传输选通信号的选通端子 信号到分配器电路。

公开(公告)号：US20060022737A1

公开(公告)日：2006-02-02

申请号：US11194510

申请日：2005-08-01

Applicant: Peter Gregorius ,  Andreas Jakobs

Inventor： Peter Gregorius ,  Andreas Jakobs

IPC: H03H11/26

CPC classification number: H03L7/0814 ,  H03K5/133 ,  H03K5/135 ,  H03K5/1565 ,  H03K2005/00019 ,  H03L7/0805

Abstract: A device for the regulated delay of a clock signal is proposed, which comprises a delay means in order to generate a delayed clock signal, and comparison means for the phase comparison of the delayed clock signal with a reference clock signal. The reference clock signal is in this connection preferably formed by the clock signal or is derived therefrom. On the basis of a comparison signal generated by the comparison means, a digital control signal is generated for controlling the delay means. The comparison means are configured so as to generate the comparison signal as a digitally coded signal that has a pulse duty ratio and a frequency that are determined by a further clock signal that is generated independently of the first clock signal, and that preferably has twice the frequency of the first clock signal.

Abstract translation: 提出了一种用于时钟信号的稳定延迟的装置，其包括延迟装置以产生延迟的时钟信号，以及用于将延迟的时钟信号与参考时钟信号进行相位比较的比较装置。 参考时钟信号优选地由时钟信号形成或从其导出。 基于由比较装置生成的比较信号，生成用于控制延迟装置的数字控制信号。 比较装置被配置为产生比较信号作为数字编码信号，该数字编码信号具有由独立于第一时钟信号产生的另外的时钟信号确定的脉冲占空比和频率，并且优选具有两倍 第一个时钟信号的频率。

公开(公告)号：US06909657B2

公开(公告)日：2005-06-21

申请号：US10675433

申请日：2003-09-30

Applicant: Andreas Jakobs ,  Thomas Janik ,  Manfred Menke ,  Eckehard Plättner

Inventor： Andreas Jakobs ,  Thomas Janik ,  Manfred Menke ,  Eckehard Plättner

IPC: G11C11/406 ,  G11C7/00

CPC classification number: G11C11/40603 ,  G11C11/406 ,  G11C11/40611

Abstract: A psuedostatic memory circuit is selected by a memory selection signal. A control circuit, in a first operating mode, carries out a refresh of the memory area at a refresh address after reception of the refresh request signal by generation of a refresh signal if the memory circuit is deselected or if, in the event of selection of the memory circuit by the memory selection signal, the access to the memory area is ended before the generation of a further refresh request signal. The control circuit, in a second operating mode, interrupts an access to the memory area for the writing and read-out of data and carries out a refresh of the memory area by generation of a refresh signal if the memory circuit is selected and a further refresh request signal is received before the ending of the access to the memory area.

Abstract translation: 通过存储器选择信号选择伪静态存储器电路。 如果取消选择存储器电路，则在第一操作模式中的控制电路在接收到刷新请求信号之后的刷新地址处刷新存储器区域，或者如果在选择 通过存储器选择信号的存储器电路，在生成另外的刷新请求信号之前结束对存储器区域的访问。 在第二操作模式中，控制电路中断对存储器区域的访问以便写入和读出数据，并且如果选择了存储器电路，则通过产生刷新信号来进行存储区域的刷新 在访问存储器区域的结束之前接收到刷新请求信号。

公开(公告)号：US20050094462A1

公开(公告)日：2005-05-05

申请号：US10949793

申请日：2004-09-24

Applicant: Andreas Jakobs

Inventor： Andreas Jakobs

IPC: G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C5/06

CPC classification number: G11C7/109 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2254

Abstract: A calibration apparatus is provided for adjusting the relative phase between two signals received at a memory chip, the two signals being generated such that they are synchronized with one another in a controller and are transmitted to the memory chip via separate lines. The calibration apparatus comprises a measuring device, which is arranged in the memory chip and is designed for measuring the relative phase between the two received signals, and a feedback loop containing a phase-controlling correction device. The measuring device is designed for generating an item of control information indicating the deviation of the measured relative phase from a defined tolerance range. The correction device responds to the control information to compensate for the deviation. The correction device is arranged in the controller and is designed for influencing the relative phase between the two signals to be transmitted to the memory chip. The feedback loop contains a signal connection leading from the memory chip to the controller.

Abstract translation: 提供了一种校准装置，用于调整在存储器芯片处接收的两个信号之间的相对相位，这两个信号被产生，使得它们在控制器中彼此同步，并通过分离的线路传送到存储器芯片。 校准装置包括测量装置，其被布置在存储器芯片中并且被设计用于测量两个接收信号之间的相对相位，以及包括相位控制校正装置的反馈回路。 测量装置被设计用于产生指示所测量的相对相位与限定的公差范围的偏差的控制信息项。 校正装置响应控制信息以补偿偏差。 校正装置被布置在控制器中，并且被设计用于影响要发送到存储器芯片的两个信号之间的相对相位。 反馈回路包含从存储芯片引导到控制器的信号连接。

公开(公告)号：US20050078532A1

公开(公告)日：2005-04-14

申请号：US10909205

申请日：2004-07-30

Applicant: Hermann Ruckerbauer ,  Maksim Kuzmenka ,  Andreas Jakobs

Inventor： Hermann Ruckerbauer ,  Maksim Kuzmenka ,  Andreas Jakobs

IPC: G11C5/06 ,  G11C7/22 ,  G11C11/4076 ,  G11C7/00

CPC classification number: G11C7/222 ,  G11C5/063 ,  G11C7/22 ,  G11C11/4076

Abstract: The invention relates to a semiconductor memory module having a plurality of memory chips and at least one buffer chip, which drives clock signals and command and address signals to the memory chips and also drives data signals to, and receives them from, the memory chips via a module-internal clock, address, command and data signal bus. The buffer chip forms an interface to an external memory main bus and the memory chips are arranged in at least one row. The memory chips have separate writing and reading clock signal inputs for receiving the clock signals and the clock signal lines are routed in at least one loop, via the memory chips, from the buffer chip to the end of each row and from there back to the buffer chip

公开(公告)号：US20050036349A1

公开(公告)日：2005-02-17

申请号：US10890934

申请日：2004-07-14

Applicant: Andreas Jakobs ,  Hermann Ruckerbauer ,  Maksim Kuzmenka

Inventor： Andreas Jakobs ,  Hermann Ruckerbauer ,  Maksim Kuzmenka

IPC: G11C5/06 ,  G11C5/02

CPC classification number: G11C29/028 ,  G11C5/063 ,  G11C29/50012

Abstract: The invention relates to a semiconductor memory module having a plurality of memory chips arranged next to one another in a row. The memory module has a module-internal clock, command/address and data bus which transfers clock signal, command and address signals and also data signals from a memory controller device to the memory chips and data signals from the memory chips to the memory controller device. The memory module has respective clock, command/address and data signal lines. The clock signal lines comprise two differential clock signal lines which, at their end opposite to the memory controller device are either open or connected to one another by a short-circuiting bridge. The memory chips, during a write operation, synchronize the write data with the clock signal running from the memory controller device to the end of the clock signal line and, during a read operation, output the read data synchronously with the clock signal reflected from the open or short-circuited end of the clock signal lines.

Abstract translation: 本发明涉及一种半导体存储器模块，该半导体存储器模块具有彼此排成一列的多个存储器芯片。 存储器模块具有模块内部时钟，命令/地址和数据总线，其将时钟信号，命令和地址信号以及数据信号从存储器控制器设备传送到存储器芯片，并将数据信号从存储器芯片传送到存储器控制器设备 。 存储器模块具有各自的时钟，命令/地址和数据信号线。 时钟信号线包括两个差分时钟信号线，它们在其与存储器控制器装置相对的端部通过短路桥断开或彼此连接。 在写入操作期间，存储器芯片将写入数据与从存储器控制器设备运行到时钟信号线的时钟信号同步，并且在读取操作期间，与从该存储器控制器设备反射的时钟信号同步地输出读取数据 开路或短路的时钟信号线。

公开(公告)号：US20050024963A1

公开(公告)日：2005-02-03

申请号：US10886814

申请日：2004-07-08

Applicant: Andreas Jakobs ,  Hermann Ruckerbauer ,  Maksim Kuzmenka

Inventor： Andreas Jakobs ,  Hermann Ruckerbauer ,  Maksim Kuzmenka

IPC: G11C5/06 ,  G11C7/10 ,  G11C11/4093 ,  G11C7/00

CPC classification number: G11C11/4093 ,  G11C5/063 ,  G11C7/10

Abstract: The invention relates to a semiconductor memory module having at least one memory chip and a buffer chip, which drives clock, address and command signals to the memory chip and drives data signals to, and receives them from, the memory chip via a module-internal clock, address, command and data bus. The buffer chip forms an interface to an external memory main bus. The data bus lines and/or the clock, command and address bus lines are respectively connected to the buffer chip at their two ends and are capable of being driven by the buffer chip from these two ends. Control means are being provided and set up in such a manner that they respectively match the directions of propagation of the data signals and of the clock, command and address signals on the corresponding bus lines during writing and reading.

Abstract translation: 本发明涉及一种具有至少一个存储器芯片和缓冲芯片的半导体存储器模块，其将时钟，地址和命令信号驱动到存储器芯片，并且经由模块内部驱动数据信号并从存储器芯片接收它们 时钟，地址，命令和数据总线。 缓冲芯片形成与外部存储器主总线的接口。 数据总线和/或时钟，命令和地址总线分别在两端分别连接到缓冲芯片，并且能够被这两端的缓冲芯片驱动。 正在提供和设置控制装置，使得它们在写入和读取期间它们分别匹配数据信号的传播方向以及相应总线上的时钟，命令和地址信号。

公开(公告)号：US06457168B1

公开(公告)日：2002-09-24

申请号：US09492655

申请日：2000-01-27

Applicant: Andreas Jakobs

Inventor： Andreas Jakobs

IPC: G06F1750

CPC classification number: H01L22/20 ,  G03F1/36 ,  H01L21/76838

Abstract: The invention relates to a method for producing structures on the surface of a semiconductor wafer, in which after the generation of a primary layout corresponding to the structures to be produced in accordance with predetermined desired physical parameters of the structures, calculation of the parasitic fault parameters that would result from the semiconductor structures after production using the primary layout, correction of the layout to suit the results of the step of calculating the parasitic fault parameters, and production of a mask based on the layout that has been corrected to suit the parasitic fault parameters, the surface of a semiconductor wafer is structured using an etching process. The structuring process leads to production- or technology-dictated deviations from the shapes that are produced on the mask based on the corrected layout, and the primary layout is corrected on the basis of the production- or technology-dictated deviations of the structures.

Abstract translation: 本发明涉及一种用于在半导体晶片的表面上制造结构的方法，其中在根据结构的预定期望物理参数产生与要生产的结构相对应的主要布局之后，计算寄生故障参数 这将由使用主要布局的生产后的半导体结构产生，校正布局以适应计算寄生故障参数的步骤的结果，以及基于已经被校正以适应寄生故障的布局的掩模的产生 参数，使用蚀刻工艺来构造半导体晶片的表面。 结构化过程导致与基于校正布局的掩模上产生的形状的生产或技术规定的偏差，并且基于生产或技术规定的结构偏差来校正主要布局。