公开(公告)号：US20060094188A1

公开(公告)日：2006-05-04

申请号：US11261820

申请日：2005-10-28

Applicant: Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

Inventor： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Dong-Hyun Kim

IPC: H01L21/336

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: Methods of fabricating a flash memory device and flash memory devices fabricated thereby are provided. One of the methods includes forming an isolation layer in a semiconductor substrate to define a plurality of parallel active regions in the semiconductor substrate. A plurality of first conductive layer patterns are formed on the active regions. The first conductive layer patterns are spaced apart from each other in a lengthwise direction of the active regions. An insulating layer is conformally formed on the semiconductor substrate and the first conductive layer patterns. A second conductive layer is formed on the insulating layer. The second conductive layer is patterned until the insulating layer is exposed to form a plurality of parallel second conductive layer patterns. The second conductive layer patterns cross the active regions and the isolation layer to overlap the first conductive layer patterns.

Abstract translation: 提供了制造闪速存储器件的方法和由此制造的闪存器件。 一种方法包括在半导体衬底中形成隔离层以在半导体衬底中限定多个平行的有源区。 在有源区上形成多个第一导电层图案。 第一导电层图案在活性区域的长度方向上彼此间隔开。 在半导体衬底和第一导电层图案上共形形成绝缘层。 在绝缘层上形成第二导电层。 图案化第二导电层直到绝缘层暴露以形成多个平行的第二导电层图案。 第二导电层图案与有源区和隔离层交叉，以与第一导电层图案重叠。

公开(公告)号：US20050031995A1

公开(公告)日：2005-02-10

申请号：US10867468

申请日：2004-06-14

Applicant: Chang-Jin Kang ,  Myeong-Cheol Kim ,  Man-Hyoung Ryoo ,  Si-Hyeung Lee ,  Doo-Youl Lee

Inventor： Chang-Jin Kang ,  Myeong-Cheol Kim ,  Man-Hyoung Ryoo ,  Si-Hyeung Lee ,  Doo-Youl Lee

IPC: G03F9/00 ,  G03F7/00 ,  G03F7/20 ,  H01L21/027 ,  H01L23/544

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.

Abstract translation: 一种集成电路半导体器件，包括形成在硅衬底的第一部分中的单元区域，所述单元区域包括形成在所述硅衬底中的第一沟槽，填充在所述第一沟槽中的第一掩埋绝缘层，形成在所述第一沟槽上的第一绝缘图案 硅衬底和形成在第一绝缘图案上的第一导电图案。 覆盖键区域形成在硅衬底的第二部分中，并且包括在硅衬底中形成的第二沟槽，形成在硅衬底上并用作覆盖键的第二绝缘图案，以及形成在第二衬底上的第二导电图案 绝缘图案，并且通过使用第二绝缘图案校正覆盖和对准误差而形成。 对准键区域形成在硅衬底的第三部分中，并且包括形成在硅衬底中并用作对准键的第三沟槽，形成在第三沟槽中的第二掩埋绝缘层和形成在第三沟槽上的第三导电图案 第二掩埋绝缘层和第三沟槽。

公开(公告)号：US06177320B1

公开(公告)日：2001-01-23

申请号：US09226961

申请日：1999-01-08

Applicant: Chang-Hyun Cho ,  Hong-Sik Jeong ,  Jae-Goo Lee ,  Chang-Jin Kang ,  Sang-Sup Jeong ,  Chul Jung ,  Chan-Ouk Jung

Inventor： Chang-Hyun Cho ,  Hong-Sik Jeong ,  Jae-Goo Lee ,  Chang-Jin Kang ,  Sang-Sup Jeong ,  Chul Jung ,  Chan-Ouk Jung

IPC: H01L21336

CPC classification number: H01L27/10844 ,  H01L21/31144 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76897 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888

Abstract: A self aligned contact pad in a semiconductor device and a method for forming the self aligned contact pad are disclosed. A bit line contact pad and a storage node contact pad are simultaneously formed by using a photoresist layer pattern having a T-shaped opening including at least two contact regions. An etch stopping layer is formed over a semiconductor substrate and over a transistor. An interlayer dielectric layer is then formed over the etch stopping layer. Next, the interlayer dielectric layer is planarized to have a planar top surface. A mask pattern having a T-shaped opening is then formed over the interlayer dielectric layer, exposing the active region and a portion of the inactive region. The interlayer dielectric layer and etch stopping layer are sequentially etched to reveal a top surface of the semiconductor substrate using the mask pattern, thereby forming a self aligned contact opening exposing a top surface of the semiconductor substrate. The mask pattern is then removed. A conductive layer is formed in the self aligned contact opening and over the interlayer dielectric layer. The conductive layer and the interlayer dielectric layer are planarization-etched to reveal a top surface of the gate mask, thereby forming at least two contact pads.

Abstract translation: 公开了半导体器件中的自对准接触焊盘和用于形成自对准接触焊盘的方法。 通过使用具有包括至少两个接触区域的T形开口的光致抗蚀剂层图案，同时形成位线接触焊盘和存储节点接触焊盘。 在半导体衬底上并在晶体管上形成蚀刻停止层。 然后在蚀刻停止层上形成层间电介质层。 接下来，层间绝缘层被平坦化以具有平坦的顶表面。 然后在层间电介质层上形成具有T形开口的掩模图案，暴露有源区和一部分非活性区。 依次蚀刻层间电介质层和蚀刻停止层，以使用掩模图案露出半导体衬底的顶表面，从而形成暴露半导体衬底的顶表面的自对准接触开口。 然后去除掩模图案。 导电层形成在自对准接触开口中以及层间电介质层之上。 对导电层和层间电介质层进行平面蚀刻以露出栅极掩模的顶表面，从而形成至少两个接触焊盘。

公开(公告)号：US08530954B2

公开(公告)日：2013-09-10

申请号：US12491529

申请日：2009-06-25

Applicant: Dong-Hyun Kim ,  Chang-Jin Kang

Inventor： Dong-Hyun Kim ,  Chang-Jin Kang

IPC: H01L29/792

CPC classification number: H01L21/28282

Abstract: Non-volatile memory devices include a tunnel insulating layer on a channel region of a substrate, a charge-trapping layer pattern on the tunnel insulating layer and a first blocking layer pattern on the charge-trapping layer pattern. Second blocking layer patterns are on the tunnel insulating layer proximate sidewalls of the charge-trapping layer pattern. The second blocking layer patterns are configured to limit lateral diffusion of electrons trapped in the charge-trapping layer pattern. A gate electrode is on the first blocking layer pattern. The second blocking layer patterns may prevent lateral diffusion of the electrons trapped in the charge-trapping layer pattern.

Abstract translation: 非易失性存储器件包括在衬底的沟道区上的隧道绝缘层，隧道绝缘层上的电荷俘获层图案和电荷俘获层图案上的第一阻挡层图案。 第二阻挡层图案位于邻近电荷俘获层图案侧壁的隧道绝缘层上。 第二阻挡层图案被配置为限制捕获在电荷俘获层图案中的电子的横向扩散。 栅电极位于第一阻挡层图案上。 第二阻挡层图案可以防止捕获在电荷俘获层图案中的电子的横向扩散。

公开(公告)号：US20100270647A1

公开(公告)日：2010-10-28

申请号：US12779300

申请日：2010-05-13

Applicant: SUNG-IL CHO ,  SEUNG-YOUNG SON ,  CHANG-JIN KANG ,  KEONG-KOO CHI ,  JI-CHUL SHIN

Inventor： SUNG-IL CHO ,  SEUNG-YOUNG SON ,  CHANG-JIN KANG ,  KEONG-KOO CHI ,  JI-CHUL SHIN

IPC: H01L29/92

CPC classification number: H01L28/91 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L21/32136 ,  H01L27/10855

Abstract: Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

Abstract translation: 提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。 例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中， 接触插塞的上表面，在着陆焊盘和第二绝缘层上形成蚀刻停止层，在蚀刻停止层上形成第三绝缘层; 通过第三绝缘层和蚀刻停止层形成第三孔以暴露着陆焊盘，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的焊盘上形成下电极，然后通过形成电介质层和上层 电极在下电极上。

公开(公告)号：US07803517B2

公开(公告)日：2010-09-28

申请号：US11590663

申请日：2006-10-31

Applicant: Sung-chan Park ,  Chang-jin Kang

Inventor： Sung-chan Park ,  Chang-jin Kang

IPC: G03F1/00 ,  B28B19/00

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144

Abstract: A method of forming a contact hole includes forming a plurality of lower patterns on a substrate. An insulation layer is formed on the lower patterns. A self-assemble induction layer is formed on the insulation layer. A recess is formed in the self-assemble induction layer in alignment with the lower patterns. A block copolymer layer is formed in the recess to form a polymer domain at a distance from a sidewall of the recess and a polymer matrix surrounding the polymer domain. The polymer domain is removed. The self-assemble induction layer is etched using the polymer matrix as a mask to form an opening through the self-assemble induction layer to expose the insulation layer. The insulation layer exposed by the opening is etched using the self-assemble induction layer as a mask so as to form a contact hole.

Abstract translation: 形成接触孔的方法包括在基板上形成多个下部图案。 在下部图案上形成绝缘层。 在绝缘层上形成自组装感应层。 在自组装感应层中形成与下部图形对准的凹部。 在凹部中形成嵌段共聚物层，以形成与凹陷的侧壁相距一定距离的聚合物结构域和围绕聚合物结构域的聚合物基体。 去除聚合物结构域。 使用聚合物基质作为掩模蚀刻自组装感应层，以通过自组装感应层形成开口以暴露绝缘层。 使用自组装感应层作为掩模蚀刻由开口暴露的绝缘层，以形成接触孔。

公开(公告)号：US07763544B2

公开(公告)日：2010-07-27

申请号：US12496108

申请日：2009-07-01

Applicant: Keun-Hee Bai ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Cheol-Kyu Lee

Inventor： Keun-Hee Bai ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Cheol-Kyu Lee

IPC: H01L21/302

CPC classification number: H01L21/0331 ,  H01L21/0332 ,  H01L21/76897

Abstract: There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a conductive material layer, a hard mask layer, and a sidewall spacer on a substrate, and forming a silicon germanium (Si1-xGex) sacrificial layer, which has a height equal to or higher than a height of at least the conductive line structure, on an entire surface of the substrate. Then, a photoresist pattern for defining a contact hole is formed on the sacrificial layer, and the sacrificial layer is dry-etched, thereby forming a contact hole for exposing the substrate. A plurality of contacts for filling the contact hole are formed using polysilicon, and the remained sacrificial layer is wet-etched. Then, the region where the sacrificial layer is removed is filled with silicon oxide, thereby forming a first interlayer insulating layer.

Abstract translation: 提供了使用硅锗牺牲层形成半导体器件的精细图案的方法，以及使用其形成自对准接触的方法。 形成半导体器件的自对准接触的方法包括在衬底上形成具有导电材料层，硬掩模层和侧壁间隔物的导电线结构，以及形成硅锗（Si1-xGex）牺牲层 ，其具有等于或高于至少导电线结构的高度的高度，在基板的整个表面上。 然后，在牺牲层上形成用于限定接触孔的光致抗蚀剂图案，并且牺牲层被干蚀刻，从而形成用于使基板曝光的接触孔。 使用多晶硅形成用于填充接触孔的多个触点，并且将残留的牺牲层湿式蚀刻。 然后，用氧化硅填充除去牺牲层的区域，从而形成第一层间绝缘层。

公开(公告)号：US07736970B2

公开(公告)日：2010-06-15

申请号：US11869400

申请日：2007-10-09

Applicant: Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

Inventor： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

IPC: H01L21/8242

CPC classification number: H01L28/91 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L21/32136 ,  H01L27/10855

Abstract: Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer, forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

Abstract translation: 提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。 例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中， 所述接触插塞的上表面在所述着陆焊盘和所述第二绝缘层上形成蚀刻停止层，在所述蚀刻停止层上形成第三绝缘层，形成通过所述第三绝缘层的第三孔和蚀刻停止层， 选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的着陆焊盘上形成下电极，然后通过在下电极上形成电介质层和上电极来形成电容器。

公开(公告)号：US07572736B2

公开(公告)日：2009-08-11

申请号：US10261595

申请日：2002-09-30

Applicant: Yun-Sook Chae ,  Ji-Soo Kim ,  Chang-jin Kang

Inventor： Yun-Sook Chae ,  Ji-Soo Kim ,  Chang-jin Kang

IPC: H01L21/302

CPC classification number: H01L21/31138 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139

Abstract: A system, method and product of dry-etching a semiconductor device are disclosed, the system having a material supply for forming a material layer on the semiconductor substrate, a pattern for disposing at least one photoresist pattern on the material layer, a dry-etching chamber for housing a dry-etching process of the material layer, a chiller for adjusting the temperature of the chamber, the semiconductor substrate, the material layer and/or the photoresist for the dry-etching process, a stage for loading the semiconductor substrate in the dry-etching chamber, and a dry-etchant supply for dry-etching the material layer while the integrity of the photoresist pattern is enhanced by the adjusted temperature.

Abstract translation: 公开了一种干法蚀刻半导体器件的系统，方法和产品，该系统具有用于在半导体衬底上形成材料层的材料供应，用于在材料层上设置至少一种光致抗蚀剂图案的图案，干蚀刻 用于容纳材料层的干蚀刻工艺的腔室，用于调节用于干蚀刻工艺的腔室温度，半导体衬底，材料层和/或光致抗蚀剂的冷却器，用于将半导体衬底加载到 干蚀刻室和用于干蚀刻材料层的干蚀刻剂供应，同时通过调节的温度增强光致抗蚀剂图案的完整性。

公开(公告)号：US07566659B2

公开(公告)日：2009-07-28

申请号：US11157435

申请日：2005-06-21

Applicant: Keun-Hee Bai ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Cheol-Kyu Lee

Inventor： Keun-Hee Bai ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Cheol-Kyu Lee

IPC: H01L21/44

CPC classification number: H01L21/0331 ,  H01L21/0332 ,  H01L21/76897

Abstract: There are provided a method of forming a fine pattern of a semiconductor device using a silicon germanium sacrificial layer, and a method of forming a self-aligned contact using the same. The method of forming a self-aligned contact of a semiconductor device includes forming a conductive line structure having a conductive material layer, a hard mask layer, and a sidewall spacer on a substrate, and forming a silicon germanium (Si1-xGex) sacrificial layer, which has a height equal to or higher than a height of at least the conductive line structure, on an entire surface of the substrate. Then, a photoresist pattern for defining a contact hole is formed on the sacrificial layer, and the sacrificial layer is dry-etched, thereby forming a contact hole for exposing the substrate. A plurality of contacts for filling the contact hole are formed using polysilicon, and the remained sacrificial layer is wet-etched. Then, the region where the sacrificial layer is removed is filled with silicon oxide, thereby forming a first interlayer insulating layer.

Abstract translation: 提供了使用硅锗牺牲层形成半导体器件的精细图案的方法，以及使用其形成自对准接触的方法。 形成半导体器件的自对准接触的方法包括在衬底上形成具有导电材料层，硬掩模层和侧壁间隔物的导电线结构，以及形成硅锗（Si1-xGex）牺牲层 ，其具有等于或高于至少导电线结构的高度的高度，在基板的整个表面上。 然后，在牺牲层上形成用于限定接触孔的光致抗蚀剂图案，并且牺牲层被干蚀刻，从而形成用于使基板曝光的接触孔。 使用多晶硅形成用于填充接触孔的多个触点，并且将残留的牺牲层湿式蚀刻。 然后，用氧化硅填充除去牺牲层的区域，从而形成第一层间绝缘层。