公开(公告)号：US08190840B2

公开(公告)日：2012-05-29

申请号：US13155404

申请日：2011-06-08

Applicant: Yu-Lan Kuo ,  Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

Inventor： Yu-Lan Kuo ,  Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC: G06F12/00 ,  G06F13/00

CPC classification number: G11C8/20 ,  G06F21/79 ,  G11C16/22

Abstract: A memory device comprises a memory array, a status register, a status-register write-protect bit and a security register. The memory array contains a number of memory blocks. The status register includes at least one protection bit indicative of a protection status of at least one corresponding block of the memory blocks. The status-register write-protect bit is coupled with the status register for preventing a state change of the at least one protection bit. The security register includes at least one register-protection bit for preventing the state change in one of the at least one protection bit of the status register and the status-register write-protect bit.

Abstract translation: 存储器件包括存储器阵列，状态寄存器，状态寄存器写保护位和安全寄存器。 存储器阵列包含许多存储器块。 状态寄存器包括至少一个指示存储块的至少一个相应块的保护状态的保护位。 状态寄存器写保护位与状态寄存器耦合以防止至少一个保护位的状态改变。 安全寄存器包括至少一个用于防止状态寄存器的至少一个保护位和状态寄存器写保护位之一的状态改变的寄存器保护位。

公开(公告)号：US08017473B2

公开(公告)日：2011-09-13

申请号：US12791656

申请日：2010-06-01

Applicant: Chun-Yi Lee ,  Harry Chuang ,  Ping-Wei Wang ,  Kong-Beng Thei

Inventor： Chun-Yi Lee ,  Harry Chuang ,  Ping-Wei Wang ,  Kong-Beng Thei

IPC: H01L21/8238

CPC classification number: H01L27/0883 ,  G11C11/412 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  Y10S438/919

Abstract: A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.

Abstract translation: 提供了包括SRAM /反相器单元的半导体结构及其形成方法，其中SRAM /反相器单元具有改善的写入裕度。 SRAM /反相器单元包括上拉PMOS器件，其包括半导体衬底上的栅极电介质，栅极电介质上的栅电极，其中栅电极包括p型杂质和n型杂质，以及形成在 源极/漏极区域。 上拉PMOS器件的器件驱动电流由于栅电极的反掺杂而降低。

公开(公告)号：US08014944B2

公开(公告)日：2011-09-06

申请号：US11457466

申请日：2006-07-14

Applicant: Chun-Yi Lee ,  Huey-Ping Cheng

Inventor： Chun-Yi Lee ,  Huey-Ping Cheng

IPC: G01C21/30

CPC classification number: G01C21/32

Abstract: A method for auto updating application program suitable for a global position system (GPS) navigator is provided. The method comprises the following steps. First, a map-update short message is sent to the GPS navigator at a client terminal from a wireless station. Then, a map-downloading program inside the GPS navigator is woken up when the GPS navigator receives the map-update short message. Then, connecting to a map server through the map-update short message when a user decides to update the map. Accordingly, a newest electronic map can be downloaded from the wireless station.

Abstract translation: 提供了一种用于自动更新适用于全球定位系统（GPS）导航仪的应用程序的方法。 该方法包括以下步骤。 首先，从无线站在客户终端向GPS导航器发送地图更新短消息。 然后，当GPS导航器接收到地图更新短消息时，GPS导航器内的地图下载程序被唤醒。 然后，当用户决定更新地图时，通过map-update短消息连接到地图服务器。 因此，可以从无线站下载最新的电子地图。

公开(公告)号：US20110074961A1

公开(公告)日：2011-03-31

申请号：US12701724

申请日：2010-02-08

Applicant: CHUN-YI LEE

Inventor： CHUN-YI LEE

IPC: H04N17/00

CPC classification number: G06T7/001 ,  G06T2207/30108 ,  H04N5/2257 ,  H04N17/002

Abstract: A method for testing a digital camera module reads a digital image from the digital camera module under test, extracts a tricolor coefficient of each pixel of the digital image to form a measurement array, and compares the measurement array with a reference array to find tricolor coefficient differences. The method extracts an edge of the digital image, processes the edge of the digital image using binarization to obtain measurement binary values, and compares the measurement binary values with reference binary values to find binary values differences. The method further compares a count of the tricolor coefficient differences with a first acceptable value, and compares a count of the binary values differences with a second acceptable value to determine quality of the digital camera module.

Abstract translation: 数字照相机模块的测试方法从被测数字摄像机模块读取数字图像，提取数字图像的每个像素的三色系数，形成测量阵列，并将测量数组与参考数组进行比较以找到三色系数 差异 该方法提取数字图像的边缘，使用二值化处理数字图像的边缘以获得测量二进制值，并将测量二进制值与参考二进制值进行比较以找到二进制值差异。 该方法进一步将三色系数差的计数与第一可接受值进行比较，并将二进制值差的计数与第二可接受值进行比较，以确定数字照相机模块的质量。

公开(公告)号：US07885129B2

公开(公告)日：2011-02-08

申请号：US12256042

申请日：2008-10-22

Applicant: Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Chun-Yi Lee

Inventor： Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Chun-Yi Lee

IPC: G11C7/00 ,  G11C29/00 ,  G11C11/50

CPC classification number: G11C29/022 ,  G11C29/02

Abstract: A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip.

Abstract translation: 提供了一种存储芯片及其操作方法。 存储器芯片包括多个焊盘。 该方法包括分别将多个第一测试信号输入到焊盘，其中对应于两个物理相邻的焊盘的第一测试信号是互补的; 将多个分别连续到第一测试信号的第二测试信号输入到焊盘，其中对应于每个焊盘的第一测试信号和第二测试信号是互补的; 以及如果所述第一测试信号和所述第二测试信号被所述存储芯片成功接收，则从所述存储器芯片输出预期数据。

公开(公告)号：US07724595B2

公开(公告)日：2010-05-25

申请号：US11970545

申请日：2008-01-08

Applicant: Yung-Feng Lin ,  Chun-Yi Lee

Inventor： Yung-Feng Lin ,  Chun-Yi Lee

IPC: G11C7/02

CPC classification number: G11C7/062 ,  G11C7/067 ,  G11C7/08 ,  G11C16/28 ,  G11C2207/063

Abstract: A current-mode sense amplifier comprises a first current mirror, a second current mirror and an amplifying circuit. The first current mirror outputs a cell current to a memory cell and duplicates the cell current to generate a mirrored cell current. The second current mirror outputs a reference current to the reference cell and duplicates the reference current to generate a mirrored reference current. The amplifying circuit comprises a first switch, second switch, third switch and fourth switch. The first switch has first and second terminals for respectively receiving the mirrored cell and reference currents. The second and third switches have first terminals respectively coupled to the first and second terminals of the first switch, and control terminals respectively coupled to the second and first terminals of the first switch. The fourth switch is connected to second terminals of the second and third switches.

Abstract translation: 电流模式读出放大器包括第一电流镜，第二电流镜和放大电路。 第一电流镜将单元电流输出到存储单元并复制单元电流以产生镜像单元电流。 第二电流镜将参考电流输出到参考单元并复制参考电流以产生镜像参考电流。 放大电路包括第一开关，第二开关，第三开关和第四开关。 第一开关具有用于分别接收镜像单元和参考电流的第一和第二端子。 第二和第三开关具有分别耦合到第一开关的第一和第二端子的第一端子和分别耦合到第一开关的第二端子和第一端子的控制端子。 第四开关连接到第二和第三开关的第二端子。

公开(公告)号：US07683991B2

公开(公告)日：2010-03-23

申请号：US11731341

申请日：2007-03-29

Applicant: Mu-Chia Lee ,  Hao-Chun Lee ,  I-Lin Wu ,  Chun-Yi Lee ,  Cheng-Hsin Chen

Inventor： Mu-Chia Lee ,  Hao-Chun Lee ,  I-Lin Wu ,  Chun-Yi Lee ,  Cheng-Hsin Chen

IPC: G02F1/1337 ,  G02F1/1343

CPC classification number: G02F1/136213 ,  G02F1/133555 ,  G02F1/133707 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/139 ,  G02F2001/134345

Abstract: A system for displaying images is disclosed. A display panel having a multi-domain pixel structure comprises a plurality of electrodes that are physically separated form one another, each defining a domain within pixel, and a capacitance element, electrically connecting the electrodes.

Abstract translation: 公开了一种用于显示图像的系统。 具有多畴像素结构的显示面板包括彼此物理分离的多个电极，每个限定像素内的畴，以及电连接电极的电容元件。

公开(公告)号：US07308376B2

公开(公告)日：2007-12-11

申请号：US11051898

申请日：2005-02-05

Applicant: Ying-Chih Lu ,  Chin-Lung Wu ,  Chun-Yi Lee ,  Chia-Hsing Lee ,  Chi-Tsung Chang ,  Ling-Hung Yu

Inventor： Ying-Chih Lu ,  Chin-Lung Wu ,  Chun-Yi Lee ,  Chia-Hsing Lee ,  Chi-Tsung Chang ,  Ling-Hung Yu

IPC: G01R27/28

CPC classification number: G06F11/263

Abstract: A computer platform automatic testing method and system is proposed, which is designed for use in conjunction with a computer platform for performing an automatic testing procedure on a computer-dedicated circuit unit installed on the computer platform, and which is characterized by the capability of performing an automatic testing procedure on a computer-dedicated circuit unit based on a user-specified set of hardware specification data about the computer platform and circuit unit under test, and the capability of automatically generating a test report that lists related data about each faulted part of the circuit unit being tested. This feature allows hardware engineers to more conveniently and efficiently correct faulted parts in the circuit unit being tested.

Abstract translation: 提出了一种计算机平台自动测试方法和系统，其设计用于与计算机平台结合使用，用于在安装在计算机平台上的计算机专用电路单元上执行自动测试程序，其特征在于执行能力 基于用户指定的关于被测试的计算机平台和电路单元的硬件规格数据集的计算机专用电路单元的自动测试程序，以及自动生成测试报告的能力，该测试报告列出关于每个故障部分的相关数据 电路单元被测试。 该功能允许硬件工程师更方便，更有效地纠正正在测试的电路单元中的故障部件。

公开(公告)号：US20060143535A1

公开(公告)日：2006-06-29

申请号：US11051898

申请日：2005-02-05

Applicant: Ying-Chih Lu ,  Chun-Lung Wu ,  Chun-Yi Lee ,  Chia-Hsing Lee ,  Chi-Tsung Chang ,  Ling-Hung Yu

Inventor： Ying-Chih Lu ,  Chun-Lung Wu ,  Chun-Yi Lee ,  Chia-Hsing Lee ,  Chi-Tsung Chang ,  Ling-Hung Yu

IPC: G06F11/00

CPC classification number: G06F11/263

Abstract: A computer platform automatic testing method and system is proposed, which is designed for use in conjunction with a computer platform for performing an automatic testing procedure on a computer-dedicated circuit unit installed on the computer platform, and which is characterized by the capability of performing an automatic testing procedure on a computer-dedicated circuit unit based on a user-specified set of hardware specification data about the computer platform and circuit unit under test, and the capability of automatically generating a test report that lists related data about each faulted part of the circuit unit being tested. This feature allows hardware engineers to more conveniently and efficiently correct faulted parts in the circuit unit being tested.

Abstract translation: 提出了一种计算机平台自动测试方法和系统，其设计用于与计算机平台结合使用，用于在安装在计算机平台上的计算机专用电路单元上执行自动测试程序，其特征在于执行能力 基于用户指定的关于被测试的计算机平台和电路单元的硬件规格数据集的计算机专用电路单元的自动测试程序，以及自动生成测试报告的能力，该测试报告列出关于每个故障部分的相关数据 电路单元被测试。 该功能允许硬件工程师更方便，更有效地纠正正在测试的电路单元中的故障部件。

公开(公告)号：US20060136794A1

公开(公告)日：2006-06-22

申请号：US11051230

申请日：2005-02-04

Applicant: Ying-chih Lu ,  Meng-Hua Cheng ,  Chun-Yi Lee ,  Lung-Hung Yu ,  Chi-Tsung Chang ,  Chia-Hsing Lee

Inventor： Ying-chih Lu ,  Meng-Hua Cheng ,  Chun-Yi Lee ,  Lung-Hung Yu ,  Chi-Tsung Chang ,  Chia-Hsing Lee

IPC: G01R31/28 ,  G06F3/00

CPC classification number: G06F13/4226 ,  G06F11/3656

Abstract: A computer peripheral connecting interface system configuration debugging method and system is proposed, which is designed for use in conjunction with a computer platform that is equipped with a particular type of peripheral connecting interface, such as a PCI (Peripheral Component Interconnect) interface, for automatically finding errors in the PCI system configurations of a group of peripheral devices connected to the PCI peripheral connecting interface, and if errors are found, capable of automatically generating an electronic error report. This fully-automatic debugging capability can help software engineers to more conveniently and efficiently correct the errors in the PCI system configurations on a computer platform.

Abstract translation: 提出了一种计算机外设连接接口系统配置调试方法和系统，其设计用于与具有特定类型的外围连接接口（例如PCI（外围组件互连）接口）的计算机平台结合使用，用于自动 在连接到PCI外围设备连接接口的一组外围设备的PCI系统配置中发现错误，并且如果发现错误，则能够自动生成电子错误报告。 这种全自动调试功能可以帮助软件工程师更方便有效地纠正计算机平台上PCI系统配置中的错误。