公开(公告)号：US20110195554A1

公开(公告)日：2011-08-11

申请号：US13089765

申请日：2011-04-19

Applicant: Yen-Sen Wang ,  Chung-Te Lin ,  Min Cao ,  Sheng-Jier Yang

Inventor： Yen-Sen Wang ,  Chung-Te Lin ,  Min Cao ,  Sheng-Jier Yang

IPC: H01L21/336

CPC classification number: H01L29/78 ,  H01L21/76802 ,  H01L21/76829 ,  H01L29/7843

Abstract: A semiconductor structure includes an active region; a gate strip overlying the active region; and a metal-oxide-semiconductor (MOS) device. A portion of the gate strip forms a gate of the MOS device. A portion of the active region forms a source/drain region of the MOS device. The semiconductor structure further includes a stressor region over the MOS device; and a stressor-free region inside the stressor region and outside the region over the active region.

Abstract translation: 半导体结构包括有源区; 覆盖有源区的栅极条; 和金属氧化物半导体（MOS）器件。 栅极条的一部分形成MOS器件的栅极。 有源区的一部分形成MOS器件的源/漏区。 半导体结构还包括MOS器件上的应力区域; 以及在应激源区域内部以及有源区域之外的区域外的无应力区域。

公开(公告)号：US20100065913A1

公开(公告)日：2010-03-18

申请号：US12212088

申请日：2008-09-17

Applicant: Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

Inventor： Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

IPC: H01L27/092 ,  G06F17/50

CPC classification number: G06F17/5068 ,  G03F1/36

Abstract: A method for forming masks for manufacturing a circuit includes providing a design of the circuit, wherein the circuit comprises a device; performing a first logic operation to determine a first region for forming a first feature of the device; and performing a second logic operation to expand the first feature to a second region greater than the first region. The pattern of the second region may be used to form the masks.

Abstract translation: 用于形成用于制造电路的掩模的方法包括提供电路的设计，其中电路包括器件; 执行第一逻辑操作以确定用于形成所述设备的第一特征的第一区域; 以及执行第二逻辑操作以将所述第一特征扩展到大于所述第一区域的第二区域。 可以使用第二区域的图案来形成掩模。

公开(公告)号：US06207538B1

公开(公告)日：2001-03-27

申请号：US09472998

申请日：1999-12-28

Applicant: Kuo-Hua Pan ,  Chu-Wei Hu ,  Chung-Te Lin ,  Chin-Hsiung Ho

Inventor： Kuo-Hua Pan ,  Chu-Wei Hu ,  Chung-Te Lin ,  Chin-Hsiung Ho

IPC: H01L2104

CPC classification number: H01L21/823892

Abstract: A method for forming both n and p wells in a semiconductor substrate using a single photolithography masking step, a non-conformal oxide layer and a chemical-mechanical polish step. A screen oxide layer is formed on a semiconductor substrate. A barrier layer is formed on the screen oxide layer. The barrier layer is patterned to form a first opening in the barrier layer over regions of the substrate where first wells will be formed. We implant impurities of a first conductivity type into the substrate to form first wells. In a key step, a non-conformal oxide layer is formed over the first well regions and the barrier layer. It is critical that the non-conformal oxide layer formed using a HDPCVD process. The non-conformal oxide layer is chemical-mechanical polished stopping at the barrier layer. The barrier layer is removed using a selective etch, to form second openings in the remaining non-conformal oxide layer over areas where second well will be formed in the substrate. Using the remaining non-conformal oxide as a mask, we implant impurities of the second conductivity type through the second openings to form second wells. The remaining non-conformal oxide layer and the screen oxide layer are removed.

Abstract translation: 一种使用单一光刻掩模步骤，非保形氧化物层和化学机械抛光步骤在半导体衬底中形成n阱和p阱的方法。 在半导体基板上形成荧光体层。 在屏幕氧化物层上形成阻挡层。 阻挡层被图案化以在衬底的形成第一阱的区域上的阻挡层中形成第一开口。 我们将第一导电类型的杂质植入衬底中以形成第一孔。 在关键步骤中，在第一阱区和阻挡层上形成非共形氧化物层。 使用HDPCVD工艺形成的非共形氧化物层是至关重要的。 非保形氧化物层在阻挡层处被化学机械抛光停止。 使用选择性蚀刻去除阻挡层，以在剩余的非保形氧化物层中在衬底中将形成第二阱的区域上形成第二开口。 使用剩余的非保形氧化物作为掩模，我们通过第二开口植入第二导电类型的杂质以形成第二孔。 去除剩余的非保形氧化物层和屏幕氧化物层。

公开(公告)号：US6080638A

公开(公告)日：2000-06-27

申请号：US244880

申请日：1999-02-05

Applicant: Chung-Te Lin ,  Shwangming Jeng ,  Yuan-Horng Chiu ,  Kong-Beng Thei

Inventor： Chung-Te Lin ,  Shwangming Jeng ,  Yuan-Horng Chiu ,  Kong-Beng Thei

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224

Abstract: A method to reduce to reduce DRAM capacitor STI junction leakage current. A Shallow Trench Isolation opening is formed, within this opening Field Oxide is deposited. The top surface of the FOX is etched down and a second layer of oxide is deposited over the FOX and the adjacent active regions. This second layer of oxide is etched bringing the top surface down to below the level of the top surface of the surrounding active areas but leaving spacers where the top surface of the FOX intersects with the active areas.

Abstract translation: 一种降低DRAM电容器STI结的漏电流的方法。 形成浅沟槽隔离开口，在该开口中形成场氧化物。 FOX的顶表面被蚀刻并且在FOX和相邻的活性区上沉积第二层氧化物。 该第二层氧化物被蚀刻，使顶部表面向下降到低于周围有效区域的顶表面的水平面，但留下FOX的顶部表面与活性区域相交的间隔物。

公开(公告)号：US08216905B2

公开(公告)日：2012-07-10

申请号：US12768063

申请日：2010-04-27

Applicant: Ru-Shang Hsiao ,  Nai-Wen Cheng ,  Chung-Te Lin ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu

Inventor： Ru-Shang Hsiao ,  Nai-Wen Cheng ,  Chung-Te Lin ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu

IPC: H01L21/336

CPC classification number: H01L27/1463 ,  H01L21/324 ,  H01L21/823878 ,  H01L22/34 ,  H01L27/14689 ,  H01L29/7842

Abstract: The active pixel cell structures and methods of preparing such structures described above enable reduction of dark current and white cell counts for active pixel cells. The process of preparing active pixel cell structures introduces stress on the substrate, which could lead to increased dark current and white cell counts of active pixel cells. By depositing a stress layer as part of a pre-metal dielectric layer with a stress that counters the stress induced, both the dark current and the white cell counts can be reduced. If the transistors of the active pixel cells are NMOS, the carrier mobility can also be increased by a tensile stress layer. Raman Spectroscopy can be used to measure the stress exerted on the substrate prior to the deposition of the stress layer.

Abstract translation: 上述有源像素单元结构和制备这种结构的方法能够减少有源像素单元的暗电流和白细胞计数。 制备有源像素单元结构的过程在衬底上引入应力，这可能导致有源像素单元的暗电流和白细胞计数增加。 通过沉积应力层作为预金属介电层的一部分，其应力引起应力，暗电流和白细胞计数都可以减小。 如果有源像素单元的晶体管是NMOS，则载流子迁移率也可以通过拉伸应力层增加。 拉曼光谱可用于测量在沉积应力层之前施加在基底上的应力。

公开(公告)号：US20100330755A1

公开(公告)日：2010-12-30

申请号：US12873889

申请日：2010-09-01

Applicant: Ru-Shang Hsiao ,  Min Cao ,  Chung-Te Lin ,  Ta-Ming Kuan ,  Cheng-Tung Hsu

Inventor： Ru-Shang Hsiao ,  Min Cao ,  Chung-Te Lin ,  Ta-Ming Kuan ,  Cheng-Tung Hsu

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors.

Abstract translation: 提供具有局部应力源的诸如PMOS晶体管的半导体器件。 凹槽形成在栅电极的相对侧上，使得凹槽通过假间隔件从栅电极偏移。 这些凹部填充有应力诱导层。 去除虚拟凹槽并形成轻掺杂的排水沟。 此后，形成新的间隔物并且应力诱导层凹陷。 可以执行一个或多个附加植入物以完成源极/漏极区域。 在一个实施例中，PMOS晶体管可以形成在与一个或多个NMOS晶体管相同的衬底上。 也可以在PMOS和/或NMOS晶体管上形成双重蚀刻停止层。

公开(公告)号：US07449386B2

公开(公告)日：2008-11-11

申请号：US11600030

申请日：2006-11-16

Applicant: Chung-Te Lin ,  Di-Houng Lee ,  Yee-Chaung See

Inventor： Chung-Te Lin ,  Di-Houng Lee ,  Yee-Chaung See

IPC: H01L21/336

CPC classification number: H01L21/823412 ,  H01L21/823418

Abstract: A method of manufacturing a plurality of MOS transistors includes forming gate structures in first and second regions on a substrate and forming mask portions only between adjacent drain sides of the respective gate structures only in the first region. Dopant of a first conductivity type that is the same as that of the substrate, is implanted at first and second angles in both the first and second regions to form halo regions only in source sides under the gate structures in the first region and in both source and drain sides under the gate structures in the second region.

Abstract translation: 制造多个MOS晶体管的方法包括在基板上的第一和第二区域中形成栅极结构，并且仅在第一区域中仅在相应栅极结构的相邻漏极侧之间形成掩模部分。 在第一和第二区域中以第一和第二角度注入与衬底相同的第一导电类型的掺杂剂，以仅在第一区域的栅极结构的源极侧和两个源中形成卤素区域 并且在第二区域中的栅极结构下方的漏极侧。

公开(公告)号：US20080258233A1

公开(公告)日：2008-10-23

申请号：US11738968

申请日：2007-04-23

Applicant: Ru-Shang Hsiao ,  Min Cao ,  Chung-Te Lin ,  Ta-Ming Kuan ,  Cheng-Tung Hsu

Inventor： Ru-Shang Hsiao ,  Min Cao ,  Chung-Te Lin ,  Ta-Ming Kuan ,  Cheng-Tung Hsu

IPC: H01L29/76

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device, such as a PMOS transistor, having localized stressors is provided. Recesses are formed on opposing sides of gate electrodes such that the recesses are offset from the gate electrode by dummy spacers. The recesses are filled with a stress-inducing layer. The dummy recesses are removed and lightly-doped drains are formed. Thereafter, new spacers are formed and the stress-inducing layer is recessed. One or more additional implants may be performed to complete source/drain regions. In an embodiment, the PMOS transistor may be formed on the same substrate as one or more NMOS transistors. Dual etch stop layers may also be formed over the PMOS and/or the NMOS transistors.

Abstract translation: 提供具有局部应力源的诸如PMOS晶体管的半导体器件。 凹槽形成在栅电极的相对侧上，使得凹槽通过假间隔件从栅电极偏移。 这些凹部填充有应力诱导层。 去除虚拟凹槽并形成轻掺杂的排水沟。 此后，形成新的间隔物并且应力诱导层凹陷。 可以执行一个或多个附加植入物以完成源极/漏极区域。 在一个实施例中，PMOS晶体管可以形成在与一个或多个NMOS晶体管相同的衬底上。 也可以在PMOS和/或NMOS晶体管上形成双重蚀刻停止层。

公开(公告)号：US07432149B2

公开(公告)日：2008-10-07

申请号：US11290914

申请日：2005-11-30

Applicant: I-Lu Wu ,  Chung-Te Lin ,  Tan-Chen Lee

Inventor： I-Lu Wu ,  Chung-Te Lin ,  Tan-Chen Lee

IPC: H01L21/8238

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/785

Abstract: Methods and structures for CMOS devices with hybrid crystal orientations using double SOI substrates is provided. In accordance with preferred embodiments, a manufacturing sequence includes the steps of forming an SOI silicon epitaxy layer after the step of forming shallow trench isolation regions. The preferred sequence allows hybrid SOI CMOS fabrication without encountering problems caused by forming STI regions after epitaxy. A preferred device includes an NFET on a {100} crystal orientation and a PFET on a {110} crystal orientation. An NMOS channel may be oriented along the direction, which is the direction of maximum electron mobility for a {100} substrate. A PMOS channel may be oriented along the direction, which is the direction where hole mobility is maximum for a {110} substrate.

Abstract translation: 提供了使用双重SOI衬底的具有混合晶体取向的CMOS器件的方法和结构。 根据优选实施例，制造顺序包括在形成浅沟槽隔离区的步骤之后形成SOI硅外延层的步骤。 优选的顺序允许混合SOI CMOS制造，而不会遇到在外延后形成STI区域引起的问题。 优选的器件包括{100}晶体取向的NFET和{110}晶体取向的PFET。 可以沿着<100>方向取向NMOS沟道，这是{100}衬底的最大电子迁移率的方向。 可以沿着<110>方向取向PMOS沟道，这是{110}衬底的空穴迁移率最大的方向。

公开(公告)号：US20080179689A1

公开(公告)日：2008-07-31

申请号：US11669870

申请日：2007-01-31

Applicant: Tan-Chen Lee ,  Chung-Te Lin ,  Kuang-Hsin Chen ,  Chi-Hsi Wu ,  Di-Houng Lee ,  Cheng-Hung Chang

Inventor： Tan-Chen Lee ,  Chung-Te Lin ,  Kuang-Hsin Chen ,  Chi-Hsi Wu ,  Di-Houng Lee ,  Cheng-Hung Chang

IPC: H01L29/78 ,  H01L21/441

CPC classification number: H01L21/28518 ,  H01L21/76829 ,  H01L29/665

Abstract: Disclosed herein are various embodiments of techniques for preventing silicide stringer or encroachment formation during metal salicide formation in semiconductor devices. The disclosed technique involves depositing a protective layer, such as a nitride or other dielectric layer, over areas of the semiconductor device where metal silicide formation is not desired because such formation detrimentally affects device performance. For example, silicon particles that may remain in device features that are formed through silicon oxidation, such as under the gate sidewall spacers and proximate to the perimeter of shallow trench isolation structures, are protected from reacting with metal deposited to form metal silicide in certain areas of the device. As a result, silicide stringers or encroachment in undesired areas is reduced or eliminated by the protective layer.

Abstract translation: 本文公开了用于在半导体器件中的金属自对准硅化物形成期间防止硅化物纵梁或侵入形成的技术的各种实施例。 所公开的技术包括在不需要金属硅化物形成的半导体器件的区域上沉积诸如氮化物或其它电介质层的保护层，因为这种形成不利地影响器件性能。 例如，可以保留在通过硅氧化形成的器件特征中的硅颗粒，例如在栅极侧壁间隔物附近并且靠近浅沟槽隔离结构的周边，防止在某些区域沉积以形成金属硅化物的金属反应 的设备。 结果，通过保护层减少或消除了硅化物桁条或侵入不期望的区域。