公开(公告)号：US08959278B2

公开(公告)日：2015-02-17

申请号：US13106703

申请日：2011-05-12

Applicant: Kun Xu ,  Tommi M. Jokinen ,  David B. Kramer

Inventor： Kun Xu ,  Tommi M. Jokinen ,  David B. Kramer

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F12/02 ,  G06F12/0284 ,  G06F2212/254

Abstract: A method of multicast data transfer including accessing a source address to a source location of mapped memory which stores source data, accessing multiple destination addresses to corresponding destination locations of the mapped memory, and for each of at least one section of the source data, reading the section using the source address, storing the section into a local memory of a data transfer device, and writing the section from the local memory to each destination location in the mapped memory using the destination addresses. Separate source and destination attributes may be provided, so that the source and each destination may have different attributes for reading and storing data. The source and each destination may have any number of data buffers accessible by corresponding links provided in data structures supporting the data transfer. The source data may be divided into sections and handled section by section.

Abstract translation: 一种组播数据传输的方法，包括：访问源地址到存储源数据的映射存储器的源位置，将多个目的地地址存取到映射存储器的相应目的地位置，以及对源数据的至少一个部分中的每一个进行读取 该部分使用源地址，将该部分存储到数据传输设备的本地存储器中，以及使用目的地地址将该部分从本地存储器写入映射的存储器中的每个目的地位置。 可以提供单独的源和目的地属性，使得源和每个目的地可以具有用于读取和存储数据的不同属性。 源和每个目的地可以具有可由支持数据传输的数据结构中提供的相应链路访问的任何数量的数据缓冲器。 源数据可以分为部分和逐段处理。

公开(公告)号：US20140281335A1

公开(公告)日：2014-09-18

申请号：US13838133

申请日：2013-03-15

Applicant: Kun Xu ,  Tommi M. Jokinen ,  David B. Kramer

Inventor： Kun Xu ,  Tommi M. Jokinen ,  David B. Kramer

IPC: G06F3/06

CPC classification number: G06F13/1631 ,  G06F13/1647 ,  G06F13/28 ,  G06F2213/16 ,  G06F2213/2806

Abstract: A communication channel controller includes a queue, a memory map, and a scheduler. The queue to store a first memory transfer request received at the communication channel controller. The memory map stores information to identify a memory address range to be associated with a memory. The scheduler to compare a source address of the first memory transfer in the queue to the memory address range in the memory map to determine whether the source address of the first memory transfer request targets the memory, and in response allocate the first memory transfer request to a first communication channel of a plurality of communication channels in response to the first communication channel having all of its outstanding memory transactions to a common source address bank and source address page as a source address bank and a source address page of the first memory transfer request.

Abstract translation: 通信信道控制器包括队列，存储器映射和调度器。 存储在通信信道控制器处接收的第一存储器传送请求的队列。 存储器映射存储用于标识与存储器相关联的存储器地址范围的信息。 调度器将队列中的第一存储器传输的源地址与存储器映射中的存储器地址范围进行比较，以确定第一存储器传送请求的源地址是否针对存储器，并且响应于将第一存储器传送请求分配给 多个通信信道的第一通信信道响应于第一通信信道具有其所有未完成的存储器事务到公共源地址组和作为源地址组的源地址页和第一存储器转移请求的源地址页 。

公开(公告)号：US20120290808A1

公开(公告)日：2012-11-15

申请号：US13106703

申请日：2011-05-12

Applicant: Kun Xu ,  Tommi M. Jokinen ,  David B. Kramer

Inventor： Kun Xu ,  Tommi M. Jokinen ,  David B. Kramer

IPC: G06F12/02

CPC classification number: G06F12/02 ,  G06F12/0284 ,  G06F2212/254

Abstract: A method of multicast data transfer including accessing a source address to a source location of mapped memory which stores source data, accessing multiple destination addresses to corresponding destination locations of the mapped memory, and for each of at least one section of the source data, reading the section using the source address, storing the section into a local memory of a data transfer device, and writing the section from the local memory to each destination location in the mapped memory using the destination addresses. Separate source and destination attributes may be provided, so that the source and each destination may have different attributes for reading and storing data. The source and each destination may have any number of data buffers accessible by corresponding links provided in data structures supporting the data transfer. The source data may be divided into sections and handled section by section.

Abstract translation: 一种组播数据传输的方法，包括：访问源地址到存储源数据的映射存储器的源位置，将多个目的地地址存取到映射存储器的相应目的地位置，以及对源数据的至少一个部分中的每一个进行读取 该部分使用源地址，将该部分存储到数据传输设备的本地存储器中，以及使用目的地地址将该部分从本地存储器写入映射的存储器中的每个目的地位置。 可以提供单独的源和目的地属性，使得源和每个目的地可以具有用于读取和存储数据的不同属性。 源和每个目的地可以具有可由支持数据传输的数据结构中提供的相应链路访问的任何数量的数据缓冲器。 源数据可以分为部分和逐段处理。

公开(公告)号：US07149211B2

公开(公告)日：2006-12-12

申请号：US10993627

申请日：2004-11-19

Applicant: Victor A. Bennett ,  Leslie Zsohar ,  Shannon E. Lawson ,  Sean W. McGee ,  David P. Sonnier ,  David B. Kramer

Inventor： Victor A. Bennett ,  Leslie Zsohar ,  Shannon E. Lawson ,  Sean W. McGee ,  David P. Sonnier ,  David B. Kramer

IPC: H04L12/50

CPC classification number: H04Q11/0478 ,  H04L49/107 ,  H04L49/3081 ,  H04L2012/5647 ,  H04L2012/5658 ,  H04L2012/5667 ,  H04L2012/5679

Abstract: A virtual reassembly system for use with a fast pattern processor and a method of operating the same. In one embodiment, the virtual reassembly system includes a first pass subsystem configured to convert a packet of a protocol data unit into at least one processing block, queue the at least one processing block based upon a header of the packet and determine if the packet is a last packet of the protocol data unit. The virtual reassembly system further includes a second pass subsystem configured to virtually reassemble the protocol data unit by retrieving the at least one processing block based upon the queue.

Abstract translation: 用于快速图案处理器的虚拟重组系统及其操作方法。 在一个实施例中，虚拟重组系统包括：第一传递子系统，被配置为将协议数据单元的分组转换成至少一个处理块，基于分组的报头对至少一个处理块进行队列，并确定分组是否 协议数据单元的最后一个分组。 虚拟重组系统还包括被配置为通过基于队列检索至少一个处理块来虚拟地重新组合协议数据单元的第二传递子系统。

公开(公告)号：US07009979B1

公开(公告)日：2006-03-07

申请号：US09822655

申请日：2001-03-30

Applicant: David B. Kramer ,  David P. Sonnier

Inventor： David B. Kramer ,  David P. Sonnier

IPC: H04L12/28

CPC classification number: H04L12/5601 ,  H04L49/90 ,  H04L49/9073 ,  H04L2012/5652 ,  H04L2012/5658 ,  H04L2012/5667 ,  H04L2012/5681

Abstract: A virtual segmentation system for use with a routing switch processor and a method of operating the same. In one embodiment, the virtual segmentation system includes a protocol data unit receiver subsystem configured to receive at least a portion of a protocol data unit and assemble the protocol data unit. The virtual segmentation system further includes a virtual segmentation subsystem that is associated with the protocol data unit receiver subsystem and is configured to perform virtual segmentation on the protocol data unit.

Abstract translation: 用于路由交换处理器的虚拟分段系统及其操作方法。 在一个实施例中，虚拟分段系统包括被配置为接收协议数据单元的至少一部分并且组合协议数据单元的协议数据单元接收器子系统。 虚拟分割系统还包括与协议数据单元接收器子系统相关联的虚拟分段子系统，并且被配置为在协议数据单元上执行虚拟分段。

公开(公告)号：US06850516B2

公开(公告)日：2005-02-01

申请号：US09798472

申请日：2001-03-02

Applicant: Victor A. Bennett ,  Leslie Zsohar ,  Shannon E. Lawson ,  Sean W. McGee ,  David P. Sonnier ,  David B. Kramer

Inventor： Victor A. Bennett ,  Leslie Zsohar ,  Shannon E. Lawson ,  Sean W. McGee ,  David P. Sonnier ,  David B. Kramer

IPC: G06F9/30 ,  G06F9/38 ,  H04L12/56 ,  H04Q11/04 ,  H04L12/50

CPC classification number: H04Q11/0478 ,  H04L49/107 ,  H04L49/3081 ,  H04L2012/5647 ,  H04L2012/5658 ,  H04L2012/5667 ,  H04L2012/5679

Abstract: A virtual reassembly system for use with a fast pattern processor and a method of operating the same. In one embodiment, the virtual reassembly system includes a first pass subsystem configured to convert a packet of a protocol data unit into at least one processing block, queue the at least one processing block based upon a header of the packet and determine if the packet is a last packet of the protocol data unit. The virtual reassembly system further includes a second pass subsystem configured to virtually reassemble the protocol data unit by retrieving the at least one processing block based upon the queue.

公开(公告)号：US09501442B2

公开(公告)日：2016-11-22

申请号：US14265847

申请日：2014-04-30

Applicant: David B. Kramer ,  Thang Q. Nguyen

Inventor： David B. Kramer ,  Thang Q. Nguyen

IPC: G06F13/368 ,  G06F13/40 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/368 ,  G06F13/4022 ,  G06F13/4221

Abstract: In an system on a chip, multiple PCIe controllers may be present in which each PCIe controller may be configured to route input data to either itself or to another PCIe controller based on a priority level of the input data. Similarly, each PCIe controller may be configured to route output data by way of its own PCIe link or that of another PCIe controller based on a scheduling order which may be based on a priority level of the buffer in which the output data is stored. In this manner, multiple PCIe controllers which, in a first mode, are capable of operating independently from each other can be configured, in a second mode, to provide multiple channels for a single PCIe link, in which each channel may correspond to a different priority level.

Abstract translation: 在芯片上的系统中，可以存在多个PCIe控制器，其中每个PCIe控制器可以被配置为基于输入数据的优先级将路由输入数据本身或另一个PCIe控制器。 类似地，每个PCIe控制器可以被配置为基于可以基于其中存储输出数据的缓冲器的优先级的调度顺序，通过其自己的PCIe链路或另一PCIe控制器的链路路由输出数据。 以这种方式，在第一模式中能够彼此独立地操作的多个PCIe控制器可以在第二模式中被配置为为单个PCIe链路提供多个信道，其中每个信道可以对应于不同的 优先级。

公开(公告)号：US20150347185A1

公开(公告)日：2015-12-03

申请号：US14288541

申请日：2014-05-28

Applicant: James C. Holt ,  Joseph P. Gergen ,  David B. Kramer ,  William C. Moyer

Inventor： James C. Holt ,  Joseph P. Gergen ,  David B. Kramer ,  William C. Moyer

IPC: G06F9/48 ,  G06F9/38

CPC classification number: H04L49/00

Abstract: A method for pipelined data stream processing of packets includes determining a task to be performed on each packet of a data stream, the task having a plurality of task portions including a first task portion. Determining the first task portion is to process a first packet. In response to determining a first storage location stores a first barrier indicator, enabling the first task portion to process the first packet and storing a second barrier indicator at the first location. Determining the first task portion is to process a second next-in-order packet. In response to determining the first location stores the second barrier indicator, preventing the first task portion from processing the second packet. In response to a first barrier clear indicator, storing the first barrier indicator at the first location, and in response, enabling the first task portion to process the second packet.

Abstract translation: 用于数据流的流水线数据流处理的方法包括确定要在数据流的每个分组上执行的任务，所述任务具有包括第一任务部分的多个任务部分。 确定第一任务部分是处理第一分组。 响应于确定第一存储位置存储第一屏障指示符，使第一任务部分能够处理第一分组并在第一位置存储第二屏障指示符。 确定第一任务部分是处理第二次序的分组。 响应于确定第一位置存储第二屏障指示符，防止第一任务部分处理第二分组。 响应于第一屏障清除指示符，将第一屏障指示器存储在第一位置处，并且作为响应，使得第一任务部分能够处理第二分组。

公开(公告)号：US20150317266A1

公开(公告)日：2015-11-05

申请号：US14265847

申请日：2014-04-30

Applicant: DAVID B. KRAMER ,  Thang Q. Nguyen

Inventor： DAVID B. KRAMER ,  Thang Q. Nguyen

IPC: G06F13/40 ,  G06F13/18 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F13/4027 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/368 ,  G06F13/4022 ,  G06F13/4221

Abstract: In an system on a chip, multiple PCIe controllers may be present in which each PCIe controller may be configured to route input data to either itself or to another PCIe controller based on a priority level of the input data. Similarly, each PCIe controller may be configured to route output data by way of its own PCIe link or that of another PCIe controller based on a scheduling order which may be based on a priority level of the buffer in which the output data is stored. In this manner, multiple PCIe controllers which, in a first mode, are capable of operating independently from each other can be configured, in a second mode, to provide multiple channels for a single PCIe link, in which each channel may correspond to a different priority level.

Abstract translation: 在芯片上的系统中，可以存在多个PCIe控制器，其中每个PCIe控制器可以被配置为基于输入数据的优先级将路由输入数据本身或另一个PCIe控制器。 类似地，每个PCIe控制器可以被配置为基于可以基于其中存储输出数据的缓冲器的优先级的调度顺序，通过其自己的PCIe链路或另一PCIe控制器的链路路由输出数据。 以这种方式，在第一模式中能够彼此独立地操作的多个PCIe控制器可以在第二模式中被配置为为单个PCIe链路提供多个信道，其中每个信道可以对应于不同的 优先级。

公开(公告)号：US09152587B2

公开(公告)日：2015-10-06

申请号：US13485120

申请日：2012-05-31

Applicant: Bryan D. Marietta ,  Gary L. Whisenhunt ,  Kumar K. Gala ,  David B. Kramer

Inventor： Bryan D. Marietta ,  Gary L. Whisenhunt ,  Kumar K. Gala ,  David B. Kramer

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: A method and circuit for a data processing system provide a partitioned interrupt controller with an efficient deferral mechanism for processing partitioned interrupt requests by executing a control instruction to encode and store a delay command (e.g., DEFER or SUSPEND) in a data payload with a hardware-inserted partition attribute (LPID) for storage to a command register (25) at a physical address (PA) retrieved from a special purpose register (46) so that the partitioned interrupt controller (14) can determine if the delay command can be performed based on local access control information.

Abstract translation: 一种用于数据处理系统的方法和电路，通过执行控制指令来编码和存储具有硬件的数据有效载荷中的延迟命令（例如，DEFER或SUSPEND）来提供具有用于处理分区中断请求的有效延迟机制的分区中断控制器 - 插入分区属性（LPID），用于存储到从专用寄存器（46）检索的物理地址（PA）处的命令寄存器（25），使得分区中断控制器（14）可以确定是否可以执行延迟命令 基于本地访问控制信息。