公开(公告)号：US20150061134A1

公开(公告)日：2015-03-05

申请号：US14290620

申请日：2014-05-29

Applicant: EUN-OK LEE ,  NAM-GUN KIM ,  GYUHWAN OH ,  HEESOOK PARK ,  HYUN-JUNG LEE ,  KYUNGHO JANG

Inventor： EUN-OK LEE ,  NAM-GUN KIM ,  GYUHWAN OH ,  HEESOOK PARK ,  HYUN-JUNG LEE ,  KYUNGHO JANG

IPC: H01L23/532

CPC classification number: H01L23/5329 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/53209 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A spacer covering a sidewall of a contact plug includes a relatively more damaged first portion and a relatively less damaged second portion. An interface of the first and second portions of the spacer is spaced apart from a metal silicide layer of the contact plug. Thus reliability of the semiconductor device may be improved. Related fabrication methods are also described.

Abstract translation: 覆盖接触塞的侧壁的间隔件包括相对更受损的第一部分和相对较少受损的第二部分。 间隔物的第一和第二部分的界面与接触塞的金属硅化物层间隔开。 因此，可以提高半导体器件的可靠性。 还描述了相关的制造方法。

公开(公告)号：US20100237423A1

公开(公告)日：2010-09-23

申请号：US12791692

申请日：2010-06-01

Applicant: Jong-Ho Yun ,  Byung-Hee Kim ,  Dae-Yong Kim ,  Hyun-Su Kim ,  Eun-Ji Jung ,  Eun-Ok Lee

Inventor： Jong-Ho Yun ,  Byung-Hee Kim ,  Dae-Yong Kim ,  Hyun-Su Kim ,  Eun-Ji Jung ,  Eun-Ok Lee

IPC: H01L27/088

CPC classification number: H01L27/10885 ,  H01L27/10876

Abstract: A semiconductor device includes a plurality of channel structures on a semiconductor substrate. A bit line groove having opposing sidewalls is defined between sidewalls of adjacent ones of the plurality of channel structures. A plurality of bit lines are formed on corresponding ones of the opposing sidewalls, and the plurality of bit lines are electrically isolated from each other

Abstract translation: 半导体器件包括半导体衬底上的多个沟道结构。 具有相对侧壁的位线槽限定在多个通道结构中的相邻侧壁之间。 多个位线形成在对置的相对的侧壁的相应的一个上，多个位线彼此电隔离

公开(公告)号：US20100109094A1

公开(公告)日：2010-05-06

申请号：US12685265

申请日：2010-01-11

Applicant: Hyun-su Kim ,  Kwang-Jin Moon ,  Sang-Woo Lee ,  Eun-Ok Lee ,  Ho-Ki Lee

Inventor： Hyun-su Kim ,  Kwang-Jin Moon ,  Sang-Woo Lee ,  Eun-Ok Lee ,  Ho-Ki Lee

IPC: H01L23/50

CPC classification number: H01L21/76855 ,  H01L21/28556 ,  H01L21/76843

Abstract: Contacts having different characteristics may be created by forming a first silicide layer over a first device region of a substrate, and then forming a second silicide layer over a second device region while simultaneously further forming the first silicide layer. A first contact hole may be formed in a dielectric layer over a first device region of a substrate. A silicide layer may then be formed in the first contact hole. A second contact hole may be formed after the first contact hole and silicide layer is formed. A second silicidation may then be performed in the first and second contact holes.

Abstract translation: 可以通过在衬底的第一器件区域上形成第一硅化物层，然后在第二器件区域上形成第二硅化物层，同时进一步形成第一硅化物层来产生具有不同特性的触点。 可以在衬底的第一器件区域上的介电层中形成第一接触孔。 然后可以在第一接触孔中形成硅化物层。 可以在形成第一接触孔和硅化物层之后形成第二接触孔。 然后可以在第一和第二接触孔中执行第二硅化。

公开(公告)号：US20090233439A1

公开(公告)日：2009-09-17

申请号：US12382008

申请日：2009-03-05

Applicant: Myung-Beom Park ,  Ki-Hag Lee ,  Hyun-Su Kim ,  Eun-Ok Lee ,  Kyoo-Chul Cho ,  Jung-Sik Choi ,  Byung-Hee Kim ,  Dae-Yong Kim

Inventor： Myung-Beom Park ,  Ki-Hag Lee ,  Hyun-Su Kim ,  Eun-Ok Lee ,  Kyoo-Chul Cho ,  Jung-Sik Choi ,  Byung-Hee Kim ,  Dae-Yong Kim

IPC: H01L21/768

CPC classification number: H01L21/28556 ,  C23C16/18 ,  H01L21/28562 ,  H01L21/76843

Abstract: A metal organic precursor represented by a formula of R1-CpML is provided onto a substrate having a conductive pattern including silicon. Here, R1 is an alkyl group substituent of Cp, R1 including methyl, ethyl, propyl, pentamethyl, pentaethyl, diethyl, dimethyl or dipropyl, Cp is cyclopentadienyl, M includes nickel (Ni), cobalt (Co), titanium (Ti), platinum (Pt) zirconium (Zr) or ruthenium (Ru), and L is at least one ligand, the at least one ligand including a carbonyl. A deposition process is performed using the metal organic precursor to form a preliminary metal silicide layer and a metal layer on the substrate. The preliminary metal silicidation layer is formed on the conductive pattern. The preliminary metal silicide layer is transformed into a metal silicide layer.

Abstract translation: 将由式R1-CpML表示的金属有机前体提供到具有包括硅的导电图案的基板上。 这里，R1是Cp的烷基取代基，R1包括甲基，乙基，丙基，五甲基，五乙基，二乙基，二甲基或二丙基，Cp是环戊二烯基，M包括镍（Ni），钴（Co），钛（Ti） 铂（Pt）锆（Zr）或钌（Ru），L是至少一种配体，所述至少一种配体包括羰基。 使用金属有机前体进行沉积工艺，以在衬底上形成初步金属硅化物层和金属层。 在导电图案上形成预备金属硅化层。 将初级金属硅化物层转变成金属硅化物层。

公开(公告)号：US20080020567A1

公开(公告)日：2008-01-24

申请号：US11777536

申请日：2007-07-13

Applicant: Eun-Ji Jung ,  Jong-Ho Yun ,  Dae-Yong Kim ,  Hyun-Su Kim ,  Byung-Hee Kim ,  Eun-Ok Lee

Inventor： Eun-Ji Jung ,  Jong-Ho Yun ,  Dae-Yong Kim ,  Hyun-Su Kim ,  Byung-Hee Kim ,  Eun-Ok Lee

IPC: H01L21/441

CPC classification number: H01L21/28097 ,  H01L29/4975 ,  H01L29/66545

Abstract: Provided are methods of manufacturing a semiconductor device. Some embodiments of such methods may include forming a preliminary gate pattern on a substrate. The preliminary gate pattern may include silicon. Methods may include forming an insulation layer pattern on the substrate after forming the preliminary gate pattern. The insulation layer pattern exposes an upper face of the preliminary gate pattern. Methods may include forming a metal layer on the upper face of the preliminary gate pattern via an electroless plating process. Methods may include forming a gate pattern including a metal silicide from a reaction between the preliminary gate pattern and the metal layer by performing a heat treatment process.

Abstract translation: 提供制造半导体器件的方法。 这种方法的一些实施例可以包括在衬底上形成初步栅极图案。 初步栅极图案可以包括硅。 方法可以包括在形成初步栅极图案之后在衬底上形成绝缘层图案。 绝缘层图案露出初步栅极图案的上表面。 方法可以包括通过化学镀处理在预选择栅极图案的上表面上形成金属层。 方法可以包括通过进行热处理工艺从预选栅极图案和金属层之间的反应形成包括金属硅化物的栅极图案。

公开(公告)号：US20070281424A1

公开(公告)日：2007-12-06

申请号：US11750699

申请日：2007-05-18

Applicant: Hyun-Su Kim ,  Dae-Yong Kim ,  Eun-Ji Jung ,  Eun-Ok Lee ,  Byung-Hee Kim ,  Jong-Ho Yun

Inventor： Hyun-Su Kim ,  Dae-Yong Kim ,  Eun-Ji Jung ,  Eun-Ok Lee ,  Byung-Hee Kim ,  Jong-Ho Yun

IPC: H01L21/336

CPC classification number: H01L29/66545 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6659

Abstract: In an embodiment a first silicon pattern and a second silicon pattern are formed on a substrate. The second silicon pattern has a lower top surface than the first silicon pattern. A first spacer covering a sidewall of the first silicon pattern is formed and a second spacer covering a sidewall of the second silicon pattern is formed. A silicide process is performed to silicidize the first silicon pattern and the second silicon pattern. Work functions of the first and second silicon patterns can be controlled and optimized by controlling the composition of the first and second silicon patterns.

Abstract translation: 在一个实施例中，在衬底上形成第一硅图案和第二硅图案。 第二硅图案具有比第一硅图案更低的顶表面。 形成覆盖第一硅图案的侧壁的第一间隔物，并且形成覆盖第二硅图案的侧壁的第二间隔物。 执行硅化处理以硅化第一硅图案和第二硅图案。 可以通过控制第一和第二硅图案的组成来控制和优化第一和第二硅图案的功能。

公开(公告)号：US20070052103A1

公开(公告)日：2007-03-08

申请号：US11515876

申请日：2006-09-06

Applicant: Ho-Ki Lee ,  Kwang-Jin Moon ,  Hyun-Su Kim ,  Sung-Tae Kim ,  Sang-Woo Lee ,  Eun-Ok Lee

Inventor： Ho-Ki Lee ,  Kwang-Jin Moon ,  Hyun-Su Kim ,  Sung-Tae Kim ,  Sang-Woo Lee ,  Eun-Ok Lee

IPC: H01L23/52

CPC classification number: H01L21/486 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76846 ,  H01L23/49894 ,  H01L2924/0002 ,  H01L2924/00

Abstract: TiN layer structures for semiconductor devices, methods of forming TiN layer structures, semiconductor devices having TiN layer structures and methods of fabricating semiconductor devices are disclosed. The TiN layer structure for a semiconductor device includes a TiN base layer and a conductive capping layer. The TiN base layer is formed on a substrate. The conductive capping layer is formed on the TiN base layer by laminating unit layers repeatedly.

Abstract translation: 公开了用于半导体器件的TiN层结构，形成TiN层结构的方法，具有TiN层结构的半导体器件和制造半导体器件的方法。 用于半导体器件的TiN层结构包括TiN基层和导电覆盖层。 TiN基层形成在基板上。 通过重复层叠单元层，在TiN基层上形成导电覆盖层。