公开(公告)号：US20080266940A1

公开(公告)日：2008-10-30

申请号：US11562122

申请日：2006-11-21

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

IPC分类号： G11C11/00 ,  H01L21/06

CPC分类号： H01L45/144 ,  G11C13/00 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/1293 ,  H01L45/14 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

摘要： A memory device includes, a first electrode element, generally planar in form, having an inner contact surface. Then there is a cylindrical cap layer, spaced from the first electrode element, and a phase change element having contact surfaces in contact with the first electrode contact surface and the cap layer, in which the lateral dimension of the phase change element is less than that of the first electrode element and the cylindrical cap layer. A second electrode element extends through the cap layer to make contact with the phase change element. Side walls aligned with the cap layer, composed of dielectric fill material, extend between the first electrode elements and the cap layer, such that the phase change element, the contact surface of the first electrode element and the side walls define a gas-filled thermal isolation cell adjacent the phase change element.

摘要翻译： 存储器件包括：第一电极元件，其大体呈平面形式，具有内部接触表面。 然后存在与第一电极元件间隔开的圆柱形盖层，以及具有与第一电极接触表面和盖层接触的接触表面的相变元件，其中相变元件的横向尺寸小于 的第一电极元件和圆柱形盖层。 第二电极元件延伸穿过盖层以与相变元件接触。 与介电填充材料构成的盖层对准的侧壁在第一电极元件和盖层之间延伸，使得相变元件，第一电极元件的接触表面和侧壁限定气体充满的热 隔离单元邻近相变元件。

公开(公告)号：US07442603B2

公开(公告)日：2008-10-28

申请号：US11465094

申请日：2006-08-16

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

IPC分类号： H01L27/13

CPC分类号： H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

摘要： A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.

摘要翻译： 制造具有用于切换可编程电阻存储器中的相位变化的限定熔化区域的电阻器随机存取存储器的过程。 该工艺最初形成了一个支柱，该支柱包括衬底主体，覆盖衬底主体的第一导电材料，覆盖第一导电材料的可编程电阻性存储器材料，覆盖在可编程电阻性存储器材料上的高选择性材料， 选择性材料。 柱中的高选择性材料在高选择性材料的两侧进行各向同性蚀刻，以在长度较小的高选择性材料的每侧产生空隙。 可编程电阻式存储器材料沉积在先前由多晶硅长度减小的限制区域中，并且可编程电阻式存储器材料沉积到先前由氮化硅材料占据的区域中。

公开(公告)号：US20080173931A1

公开(公告)日：2008-07-24

申请号：US11625216

申请日：2007-01-19

申请人： ChiaHua Ho ,  Erh-Kun Lai

发明人： ChiaHua Ho ,  Erh-Kun Lai

IPC分类号： H01L27/00 ,  H01L21/44

CPC分类号： H01L45/04 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1633

摘要： The present invention provides multilevel-cell memory structures with multiple memory layer structures where each memory layer structure includes a tungsten oxide region that defines different read current levels for a plurality of logic states. Each memory layer structure can provide two bits of information, which constitutes four logic states, by the use of the tungsten oxide region that provides multilevel-cell function in which the four logic states equate to four different read current levels. A memory structure with two memory layer structures would provide four bits of storage sites and 16 logic states. In one embodiment, each of the first and second memory layer structures includes a tungsten oxide region extending into a principle surface of a tungsten plug member where the outer surface of the tungsten plug is surrounded by a barrier member.

摘要翻译： 本发明提供具有多个存储层结构的多电平单元存储器结构，其中每个存储层结构包括为多个逻辑状态定义不同读取电流电平的氧化钨区域。 每个存储器层结构可以通过使用提供多电平单元功能的氧化钨区域来提供构成四个逻辑状态的两位信息，其中四个逻辑状态等于四个不同的读取电流电平。 具有两个存储器层结构的存储器结构将提供四位存储位置和16个逻辑状态。 在一个实施例中，第一和第二存储层结构中的每一个包括延伸到钨插塞构件的主表面中的钨氧化物区域，其中钨插塞的外表面被阻挡构件包围。

公开(公告)号：US20080135824A1

公开(公告)日：2008-06-12

申请号：US11567978

申请日：2006-12-07

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

IPC分类号： H01L47/00 ,  H01L21/00

CPC分类号： G11C13/0016 ,  G11C11/5664 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0014 ,  H01L45/04 ,  H01L45/124 ,  H01L45/146 ,  H01L45/1633

摘要： A method and structure of a bistable resistance random access memory comprise a plurality of programmable resistance random access memory cells where each programmable resistance random access memory cell includes multiple memory members for performing multiple bits for each memory cell The bistable RRAM includes a first resistance random access member connected to a second resistance random access member through interconnect metal liners and metal oxide strips. The first resistance random access member has a first resistance value Ra, which is determined from the thickness of the first resistance random access member based on the deposition of the first resistance random access member. The second resistance random access member has a second resistance value Rb, which is determined from the thickness of the second resistance random access member based on the deposition of the second resistance random access member.

摘要翻译： 双稳态电阻随机存取存储器的方法和结构包括多个可编程电阻随机存取存储器单元，其中每个可编程电阻随机存取存储单元包括用于为每个存储单元执行多位的多个存储器构件。双稳态RRAM包括第一电阻随机存取 构件通过互连金属衬垫和金属氧化物条连接到第二电阻随机存取构件。 第一电阻随机存取构件具有基于第一电阻随机存取构件的沉积从第一电阻随机存取构件的厚度确定的第一电阻值Ra。 第二电阻随机存取部件具有基于第二电阻随机存取部件的沉积从第二电阻随机存取部件的厚度确定的第二电阻值Rb。

公开(公告)号：US20080096344A1

公开(公告)日：2008-04-24

申请号：US11552356

申请日：2006-10-24

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

IPC分类号： H01L21/8239

CPC分类号： H01L45/04 ,  H01L27/24 ,  H01L45/145

摘要： A method for manufacturing a resistor random access memory with a self-aligned air gap insulator. A high density plasma deposition on the stack of post-patterned layers produces a hard mask that is substantially near the center and overlying the cap layer of the stack of post-patterned layers. The high density plasma deposition is performed with small critical dimensions so that a small triangle is generated over the cap layer and located near the center of the cap layer. The hard mask serves to prevent the area directly underneath the base of the hard mask from etching, while the hard mask provides a self-aligned technique for etching the left and right sections of the stack of post-patterned layers because the hard mask overlies and positions near the center of the stack of post-patterned layers.

摘要翻译： 一种制造具有自对准气隙绝缘体的电阻随机存取存储器的方法。 在后图案化层的堆叠上的高密度等离子体沉积产生基本上靠近中心并且覆盖后图案化层的堆叠的盖层的硬掩模。 以小的临界尺寸执行高密度等离子体沉积，使得在盖层上产生小的三角形并且位于盖层的中心附近。 硬掩模用于防止硬掩模底部正下方的区域进行蚀刻，而硬掩模提供自对准技术，用于蚀刻后图案化层的堆叠的左侧和右侧部分，因为硬掩模覆盖并且 靠近堆叠的后图案化层的中心的位置。

公开(公告)号：US20080094885A1

公开(公告)日：2008-04-24

申请号：US11552433

申请日：2006-10-24

申请人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： G11C11/00

CPC分类号： G11C11/16 ,  B82Y10/00 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/0069 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/77 ,  H01L45/04 ,  H01L45/145

摘要： A bistable resistance random access memory comprises a plurality of memory cells where each memory cell having multiple memory layer stack. Each memory layer stack includes a conductive layer overlying a programmable resistance random access memory layer. A first memory layer stack overlies a second memory layer stack, and the second memory stack overlies a third memory layer stack. The first memory layer stack has a first conductive layer overlies a first programmable resistance random access memory layer. The second memory layer stack has a second conductive layer overlies a second programmable resistance random access memory layer. The second programmable resistance random access memory layer has a memory area that is larger than a memory area of the first programmable resistance random access memory layer.

摘要翻译： 双稳态电阻随机存取存储器包括多个存储单元，其中每个存储单元具有多个存储层堆栈。 每个存储层堆叠包括覆盖可编程电阻随机存取存储层的导电层。 第一存储层堆栈覆盖第二存储层堆栈，并且第二存储器堆栈覆盖第三存储层堆栈。 第一存储层堆叠具有覆盖在第一可编程电阻随机存取存储器层上的第一导电层。 第二存储层堆叠具有覆盖在第二可编程电阻随机存取存储器层上的第二导电层。 第二可编程电阻随机存取存储器层具有大于第一可编程电阻随机存取存储层的存储区的存储区。

公开(公告)号：US20080002477A1

公开(公告)日：2008-01-03

申请号：US11836142

申请日：2007-08-09

申请人： Tzu-Hsuan Hsu ,  Erh-Kun Lai ,  Hang-Ting Lue ,  Chia-Hua Ho

发明人： Tzu-Hsuan Hsu ,  Erh-Kun Lai ,  Hang-Ting Lue ,  Chia-Hua Ho

IPC分类号： G11C11/34 ,  H01L21/36

CPC分类号： H01L29/7923 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42352

摘要： The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory comprises a straddle gate, a carrier trapping layer and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping layer is located between the straddle gate and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.

摘要翻译： 本发明涉及在其上形成有多个浅沟槽隔离物的衬底上的存储单元，其中浅沟槽隔离物的顶表面低于衬底的顶表面，并且浅沟槽隔离件一起限定垂直鳍状结构 底物。 存储器包括跨骑门，载体俘获层和至少两个源极/漏极区域。 跨门位于基板上，跨越垂直翅片结构。 载体捕获层位于跨门和基板之间。 源极/漏极区域位于由跨门暴露的衬底的垂直鳍结构的一部分中。

公开(公告)号：US20070278529A1

公开(公告)日：2007-12-06

申请号：US11421036

申请日：2006-05-30

申请人： Erh Kun Lai ,  Chia Hua Ho ,  Kuang Yeu Hsieh

发明人： Erh Kun Lai ,  Chia Hua Ho ,  Kuang Yeu Hsieh

IPC分类号： H01L27/10 ,  H01L21/8234

CPC分类号： H01L45/04 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/14 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

摘要： A phase change random access memory PCRAM device is described suitable for use in large-scale integrated circuits. An exemplary memory device has a pipe-shaped first electrode formed from a first electrode layer on a sidewall of a sidewall support structure. A sidewall spacer insulating member is formed from a first oxide layer and a second, “L-shaped,” electrode is formed on the insulating member. An electrical contact is connected to the horizontal portion of the second electrode. A bridge of memory material extends from a top surface of the first electrode to a top surface of the second electrode across a top surface of the sidewall spacer insulating member.

摘要翻译： 描述适用于大规模集成电路的相变随机存取存储器PCRAM器件。 示例性存储器件具有由侧壁支撑结构的侧壁上的第一电极层形成的管状第一电极。 侧壁间隔绝缘部件由第一氧化物层形成，第二“L”形电极形成在绝缘部件上。 电触头连接到第二电极的水平部分。 记忆材料桥从第一电极的顶表面延伸到第二电极的顶表面，跨过侧壁间隔绝缘件的顶表面。

公开(公告)号：US20070262388A1

公开(公告)日：2007-11-15

申请号：US11382422

申请日：2006-05-09

申请人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Hsieh

发明人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Hsieh

IPC分类号： H01L23/62 ,  H01L21/338

CPC分类号： H01L45/04 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

摘要： A resistance random access memory in a bridge structure is disclosed that comprises a contact structure where first and second electrodes are located within the contact structure. The first electrode has a circumferential extending shape, such as an annular shape, surrounding an inner wall of the contact structure. The second electrode is located within an interior of the circumferential extending shape and separated from the first electrode by an insulating material. A resistance memory bridge is in contact with an edge surface of the first and second electrodes. The first electrode in the contact structure is connected to a transistor and the second electrode in the contact structure is connected to a bit line. A bit line is connected to the second electrode by a self-aligning process.

摘要翻译： 公开了一种桥结构中的电阻随机存取存储器，其包括其中第一和第二电极位于接触结构内的接触结构。 第一电极具有围绕接触结构的内壁的周向延伸形状，例如环形形状。 第二电极位于周向延伸形状的内部，并通过绝缘材料与第一电​​极分离。 电阻记忆桥与第一和第二电极的边缘表面接触。 接触结构中的第一电极连接到晶体管，并且接触结构中的第二电极连接到位线。 位线通过自对准工艺连接到第二电极。

公开(公告)号：US20070173019A1

公开(公告)日：2007-07-26

申请号：US11426213

申请日：2006-06-23

申请人： ChiaHua Ho ,  Erh-kun Lai ,  Kuang Hsieh

发明人： ChiaHua Ho ,  Erh-kun Lai ,  Kuang Hsieh

IPC分类号： H01L21/336

CPC分类号： H01L27/24 ,  H01L28/26

摘要： Programmable resistive RAM cells have a resistance that depends on the size of the contacts. Manufacturing methods and integrated circuits for lowered contact resistance are disclosed that have contacts of reduced size.

摘要翻译： 可编程电阻RAM单元具有取决于触点尺寸的电阻。 公开了具有降低的接触电阻的制造方法和集成电路，其具有减小的尺寸的接触。