公开(公告)号：US20130088460A1

公开(公告)日：2013-04-11

申请号：US13563911

申请日：2012-08-01

Applicant: Seung-eon Ahn ,  I-hun Song ,  Sang-hun Jeon ,  Chang-jung Kim ,  Young Kim ,  Yong-woo Jeon

Inventor： Seung-eon Ahn ,  I-hun Song ,  Sang-hun Jeon ,  Chang-jung Kim ,  Young Kim ,  Yong-woo Jeon

IPC: G06F3/042

CPC classification number: G06F3/042 ,  G06F3/0412

Abstract: An optical touch screen apparatus that includes a display pixel including a display cell and a driving transistor, the display cell configured to display an image and the driving transistor configured to turn on or off the display cell, the driving transistor having a double gate structure; and a light-sensing pixel including a light-sensing transistor and a switch transistor, the light-sensing transistor configured to sense incident light and the switch transistor configured to output data from the light-sensing transistor, the switch transistor having the double gate structure, wherein the double gate structure is a structure in which a bottom gate and a top gate are arranged such that a channel layer is disposed therebetween. The top gate may be formed together when forming a transparent electrode in the pixel, and thus even when the top gate is further included, the number of manufacturing processes is not increased.

Abstract translation: 一种光学触摸屏设备，包括包括显示单元和驱动晶体管的显示像素，所述显示单元被配置为显示图像，所述驱动晶体管被配置为导通或关闭所述显示单元，所述驱动晶体管具有双栅极结构; 以及包括感光晶体管和开关晶体管的感光像素，所述感光晶体管被配置为检测入射光，并且所述开关晶体管被配置为从所述感光晶体管输出数据，所述开关晶体管具有所述双栅极结构 其特征在于，所述双栅极结构是这样的结构，其中底栅极和顶栅极布置成使得沟道层位于它们之间。 当在像素中形成透明电极时，顶栅可以一起形成，因此即使当进一步包括顶栅时，制造工艺的数量也不会增加。

公开(公告)号：US08384439B2

公开(公告)日：2013-02-26

申请号：US12591701

申请日：2009-11-30

Applicant: Jae-chul Park ,  I-hun Song ,  Young-soo Park ,  Kee-won Kwon ,  Chang-jung Kim ,  Kyoung-kook Kim ,  Sung-ho Park ,  Sung-hoon Lee ,  Sang-wook Kim ,  Sun-il Kim

Inventor： Jae-chul Park ,  I-hun Song ,  Young-soo Park ,  Kee-won Kwon ,  Chang-jung Kim ,  Kyoung-kook Kim ,  Sung-ho Park ,  Sung-hoon Lee ,  Sang-wook Kim ,  Sun-il Kim

IPC: H01L25/00 ,  H03K19/00

CPC classification number: H01L29/7869 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11807 ,  H01L27/1225 ,  H01L27/1251 ,  H01L29/41733 ,  H01L29/78648

Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device may be a complementary device including a p-type oxide TFT and an n-type oxide TFT. The semiconductor device may be a logic device such as an inverter, a NAND device, or a NOR device.

Abstract translation: 提供半导体器件和制造半导体器件的方法。 半导体器件可以是包括p型氧化物TFT和n型氧化物TFT的互补器件。 半导体器件可以是诸如逆变器，NAND器件或NOR器件的逻辑器件。

公开(公告)号：US20130009145A1

公开(公告)日：2013-01-10

申请号：US13404136

申请日：2012-02-24

Applicant: Sang-hun JEON ,  I-hun SONG ,  Seung-eon AHN ,  Chang-jung KIM ,  Young KIM

Inventor： Sang-hun JEON ,  I-hun SONG ,  Seung-eon AHN ,  Chang-jung KIM ,  Young KIM

IPC: H01L29/12 ,  H01L21/336

CPC classification number: H01L27/14692 ,  H01L27/14612

Abstract: A transistor may include an active layer having a plurality of oxide semiconductor layers and an insulating layer disposed therebetween. The insulating layer may include a material that has higher etch selectivity with respect to at least one of the plurality of oxide semiconductor layers. The electronic device may include a first transistor and a second transistor connected to the first transistor. The second transistor may include an active layer having a different structure from that of the active layer included in the first transistor. The active layer of the second transistor may have the same structure as one of the plurality of oxide semiconductor layers constituting the active layer of the first transistor.

Abstract translation: 晶体管可以包括具有多个氧化物半导体层的有源层和设置在其间的绝缘层。 绝缘层可以包括相对于多个氧化物半导体层中的至少一个具有较高蚀刻选择性的材料。 电子设备可以包括连接到第一晶体管的第一晶体管和第二晶体管。 第二晶体管可以包括具有与包括在第一晶体管中的有源层的结构不同的结构的有源层。 第二晶体管的有源层可以具有与构成第一晶体管的有源层的多个氧化物半导体层中的一个相同的结构。

公开(公告)号：US20120282734A1

公开(公告)日：2012-11-08

申请号：US13552185

申请日：2012-07-18

Applicant: Sun-il KIM ,  Jae-cheol Lee ,  I-hun Song ,  Young-soo Park ,  Chang-jung Kim ,  Jae-chul Park

Inventor： Sun-il KIM ,  Jae-cheol Lee ,  I-hun Song ,  Young-soo Park ,  Chang-jung Kim ,  Jae-chul Park

IPC: H01L21/36 ,  H01L21/336

CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02581 ,  H01L29/78696

Abstract: An oxide thin film transistor and a method of manufacturing the oxide TFT are provided. The oxide thin film transistor (TFT) including: a gate; a channel formed to correspond to the gate, and a capping layer having a higher work function than the channel; a gate insulator disposed between the gate and the channel; and a source and drain respectively contacting either side of the capping layer and the channel and partially on a top surface of the capping layer.

Abstract translation: 提供氧化物薄膜晶体管和制造氧化物TFT的方法。 所述氧化物薄膜晶体管（TFT）包括：栅极; 形成为对应于所述栅极的沟道，以及具有比所述沟道更高功函数的覆盖层; 设置在栅极和沟道之间的栅极绝缘体; 以及源极和漏极，分别接触封盖层的两侧和通道之间，部分地接合覆盖层的顶表面。

公开(公告)号：US20110284722A1

公开(公告)日：2011-11-24

申请号：US12926831

申请日：2010-12-13

Applicant: Seung-eon Ahn ,  Sung-ho Park ,  I-hun Song ,  Sang-hun Jeon

Inventor： Seung-eon Ahn ,  Sung-ho Park ,  I-hun Song ,  Sang-hun Jeon

IPC: H01L27/146 ,  H01J40/14

CPC classification number: H03K17/78 ,  H03K17/941

Abstract: Example embodiments are directed to a light-sensing circuit, a method of operating the light-sensing circuit, and a light-sensing apparatus including the light-sensing circuit. The light-sensing circuit includes a light-sensitive oxide semiconductor transistor that senses light; and a switching transistor connected to the light-sensing transistor in series and configured to output data. During a standby time, a low voltage is applied to the switching transistor and a high voltage is applied to the light-sensitive oxide semiconductor transistor, and when data is output, the high voltage is applied to the switching transistor and the low voltage is applied to the light-sensitive oxide semiconductor transistor.

Abstract translation: 示例性实施例涉及光感​​测电路，操作光感测电路的方法以及包括光感测电路的光感测设备。 感光电路包括感测光的光敏氧化物半导体晶体管; 以及串联连接到感光晶体管并被配置为输出数据的开关晶体管。 在待机时间期间，低电压被施加到开关晶体管，并且高电压被施加到光敏氧化物半导体晶体管，并且当数据被输出时，高电压被施加到开关晶体管并施加低电压 到光敏氧化物半导体晶体管。

公开(公告)号：US20110241989A1

公开(公告)日：2011-10-06

申请号：US12923243

申请日：2010-09-10

Applicant: Sung-ho Park ,  Sang-hun Jeon ,  I-hun Song ,  Chang-jung Kim ,  Seung-eon Ahn

Inventor： Sung-ho Park ,  Sang-hun Jeon ,  I-hun Song ,  Chang-jung Kim ,  Seung-eon Ahn

IPC: G06F3/033

CPC classification number: G06F3/0386 ,  G06F3/0412

Abstract: A remote touch panel includes a plurality of light sensor cells arranged in two dimensions. Each light sensor cell may include a light-sensitive semiconductor layer and first and second electrodes electrically connected to the light-sensitive semiconductor layer. The remote touch panel may be controlled at a remote distance. For example, a large display apparatus can be easily controlled by using a simple light source device, for example, a laser pointer.

Abstract translation: 远程触摸面板包括以二维布置的多个光传感器单元。 每个光传感器单元可以包括光敏半导体层和电连接到光敏半导体层的第一和第二电极。 远程触摸面板可以被控制在远处。 例如，通过使用简单的光源装置，例如激光指示器，可以容易地控制大型的显示装置。

公开(公告)号：US07897412B2

公开(公告)日：2011-03-01

申请号：US11438211

申请日：2006-05-23

Applicant: Sang-jin Park ,  Tae-wan Kim ,  Jung-hyun Lee ,  Wan-jun Park ,  I-hun Song

Inventor： Sang-jin Park ,  Tae-wan Kim ,  Jung-hyun Lee ,  Wan-jun Park ,  I-hun Song

IPC: H01L31/062

CPC classification number: B82Y25/00 ,  B82Y10/00 ,  B82Y40/00 ,  G11C11/16 ,  H01F10/3254 ,  H01F41/307 ,  H01L27/228

Abstract: In a magnetic random access memory (MRAM) having a transistor and a magnetic tunneling junction (MTJ) layer in a unit cell, the MTJ layer includes a lower magnetic layer, an oxidation preventing layer, a tunneling oxide layer, and an upper magnetic layer, which are sequentially stacked. The tunneling oxide layer may be formed using an atomic layer deposition (ALD) method. At least the oxidation preventing layer may be formed using a method other than the ALD method.

Abstract translation: 在单元中具有晶体管和磁隧道结（MTJ）层的磁性随机存取存储器（MRAM）中，MTJ层包括下磁层，防氧化层，隧道氧化物层和上磁层 ，顺序堆叠。 隧道氧化物层可以使用原子层沉积（ALD）方法形成。 至少防氧化层可以使用除ALD法以外的方法形成。

公开(公告)号：US07893431B2

公开(公告)日：2011-02-22

申请号：US11785269

申请日：2007-04-17

Applicant: Chang-jung Kim ,  I-hun Song ,  Dong-hun Kang ,  Young-soo Park

Inventor： Chang-jung Kim ,  I-hun Song ,  Dong-hun Kang ,  Young-soo Park

IPC: H01L29/12

CPC classification number: H01L29/7869

Abstract: A semiconductor device may include a composite represented by Formula 1 below as an active layer. x(Ga2O3)·y(In2O3)·z(ZnO)  Formula 1 wherein, about 0.75≦x/z≦ about 3.15, and about 0.55≦y/z≦ about 1.70. Switching characteristics of displays and driving characteristics of driving transistors may be improved by adjusting the amounts of a gallium (Ga) oxide and an indium (In) oxide mixed with a zinc (Zn) oxide and improving optical sensitivity.

Abstract translation: 半导体器件可以包括由下面的式1表示的复合物作为有源层。 x（Ga 2 O 3）·y（In 2 O 3）·z（ZnO）式1其中约0.75＆lt; 1E; x / z＆ 约3.15，约0.55＆nlE; y / z＆nlE; 约1.70。 可以通过调节与锌（Zn）氧化物混合的镓（Ga）氧化物和铟（In））的量来提高驱动晶体管的开关特性并提高光学灵敏度。

公开(公告)号：US07682758B2

公开(公告)日：2010-03-23

申请号：US11441835

申请日：2006-05-26

Applicant: Suk-pil Kim ,  I-hun Song ,  Young-soo Park ,  Seung-hyuk Chang ,  Hoon Kim

Inventor： Suk-pil Kim ,  I-hun Song ,  Young-soo Park ,  Seung-hyuk Chang ,  Hoon Kim

IPC: G03F1/00

CPC classification number: G21K1/062 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/24

Abstract: A reflection mask for extreme ultraviolet (EUV) photolithography and a method of fabricating the same, in which the reflection mask includes a substrate, a lower reflection layer formed in a multi-layer structure on the substrate and including a material reflecting EUV light, an upper reflection layer formed in a multi-layer structure on the lower reflection layer and reflecting EUV light, and a phase reversing layer formed between the lower reflection layer and the upper reflection layer in a certain pattern and causing destructive interference between reflection light from the upper reflection layer and reflection light from the lower reflection layer. An incidence of a shadow effect can be reduced and unnecessary EUV light can be eliminated, so that a pattern on the reflection mask can be projected precisely on a silicon wafer. Since the phase reversing layer includes the same material as the reflection layer and an absorption layer, mask fabrication processes can be handled easily.

Abstract translation: 一种用于极紫外（EUV）光刻的反射掩模及其制造方法，其中反射掩模包括基板，在基板上形成为多层结构的下反射层，并且包括反射EUV光的材料， 在下反射层上形成多层结构并反射EUV光的上反射层和以一定图案形成在下反射层和上反射层之间的相位反转层，并且产生来自上层的反射光之间的相消干涉 反射层和来自下反射层的反射光。 可以减少阴影效应的入射，并且可以消除不必要的EUV光，使得反射掩模上的图案可以精确地投影在硅晶片上。 由于相位反转层包括与反射层和吸收层相同的材料，因此可以容易地处理掩模制造工艺。

公开(公告)号：US20100006834A1

公开(公告)日：2010-01-14

申请号：US12458491

申请日：2009-07-14

Applicant: Sun-il Kim ,  I-hun Song ,  Chang-jung Kim ,  Jae-chul Park ,  Sang-wook Kim

Inventor： Sun-il Kim ,  I-hun Song ,  Chang-jung Kim ,  Jae-chul Park ,  Sang-wook Kim

IPC: H01L29/26 ,  H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/78696

Abstract: Channel layers and semiconductor devices including the channel layers are disclosed. A channel layer may include a multi-layered structure. Layers forming the channel layer may have different carrier mobilities and/or carrier densities. The channel layer may have a double layered structure including a first layer and a second layer which may be formed of different oxides. Characteristics of the transistor may vary according to materials used to form the channel layers and/or thicknesses thereof.

Abstract translation: 公开了包括沟道层的通道层和半导体器件。 沟道层可以包括多层结构。 形成沟道层的层可具有不同的载流子迁移率和/或载流子密度。 沟道层可以具有双层结构，其包括可由不同氧化物形成的第一层和第二层。 晶体管的特性可以根据用于形成沟道层的材料和/或其厚度而变化。