公开(公告)号：US07226708B2

公开(公告)日：2007-06-05

申请号：US11154265

申请日：2005-06-15

申请人： J. Brett Rolfson

发明人： J. Brett Rolfson

IPC分类号： G03F1/00

CPC分类号： G03F1/32 ,  G03F1/29

摘要： The present invention provides an attenuated phase shift mask (“APSM”) that, in each embodiment, includes completely transmissive regions sized and shaped to define desired semiconductor device features, slightly attenuated regions at the edges of the completely transmissive regions corresponding to isolated device features, highly attenuated regions at the edges of completely transmissive regions corresponding to closely spaced or nested device features, and completely opaque areas where it is desirable to block transmission of all radiation through the APSM. The present invention further provides methods for fabricating the APSMs according to the present invention.

摘要翻译： 本发明提供了衰减相移掩模（“APSM”），其在每个实施例中包括尺寸和形状以确定期望的半导体器件特征的完全透射区域，在完全透射区域的边缘处对应于隔离的器件特征的略微衰减的区域 在完全透射区域的边缘处的高度衰减的区域对应于紧密间隔或嵌套的器件特征，以及完全不透明的区域，其中期望阻止通过APSM的所有辐射的透射。 本发明还提供了制造根据本发明的APSM的方法。

公开(公告)号：US07147974B2

公开(公告)日：2006-12-12

申请号：US10686342

申请日：2003-10-14

申请人： Randall W. Chance ,  J. Brett Rolfson ,  Azeddine Zerrade

发明人： Randall W. Chance ,  J. Brett Rolfson ,  Azeddine Zerrade

IPC分类号： G01F9/00

CPC分类号： G03F1/32 ,  C03C15/00 ,  G03F1/26 ,  G03F1/72

摘要： The invention includes methods of converting reticles from configurations suitable for utilization with later generation (shorter wavelength) stepper radiations to configurations suitable for utilization with earlier generation (longer wavelength) stepper radiations. The invention can be utilized for converting a reticle from a configuration suitable for 193 nanometer wavelength radiation to a configuration suitable for 248 nanometer wavelength radiation. In such aspect, a quartz-containing material of a substrate can be protected with a patterned layer consisting essentially of molybdenum and silicon while the quartz-containing material is subjected to a dry etch. The configuration suitable for 248 nanometer wavelength radiation can be constructed so that a phase of 248 nanometer wavelength radiation is shifted by about 180° upon passing through combined thicknesses of the patterned layer and the quartz-containing material, relative to 248 nanometer wavelength radiation which passes only through the quartz-containing material.

摘要翻译： 本发明包括从适合于利用后代（较短波长）步进辐射的配置转换掩模版到适于利用早期生成（更长波长）步进辐射的配置的方法。 本发明可用于将掩模版从适于193纳米波长辐射的配置转换成适合于248纳米波长辐射的配置。 在这种方面，可以用基本上由钼和硅组成的图案层来保护衬底的含石英材料，同时对含石英的材料进行干蚀刻。 可以构造适合于248纳米波长辐射的配置，使得248纳米波长辐射的相位相对于通过图案化层和含石英的材料的组合厚度相对于相对于通过的248纳米波长辐射而偏移大约180度 仅通过含石英材料。

公开(公告)号：US06908715B2

公开(公告)日：2005-06-21

申请号：US10629641

申请日：2003-07-29

申请人： J. Brett Rolfson

发明人： J. Brett Rolfson

IPC分类号： G03F1/00 ,  G03F1/32 ,  G03F9/00

CPC分类号： G03F1/32 ,  G03F1/29

摘要： The present invention provides an attenuated phase shift mask (“APSM”) that, in each embodiment, includes completely transmissive regions sized and shaped to define desired semiconductor device features, slightly attenuated regions at the edges of the completely transmissive regions corresponding to isolated device features, highly attenuated regions at the edges of completely transmissive regions corresponding to closely spaced or nested device features, and completely opaque areas where it is desirable to block transmission of all radiation through the APSM. The present invention further provides methods for fabricating the APSMs according to the present invention.

摘要翻译： 本发明提供了衰减相移掩模（“APSM”），其在每个实施例中包括尺寸和形状以确定期望的半导体器件特征的完全透射区域，在完全透射区域的边缘处对应于隔离的器件特征的略微衰减的区域 在完全透射区域的边缘处的高度衰减的区域对应于紧密间隔或嵌套的器件特征，以及完全不透明的区域，其中期望阻止通过APSM的所有辐射的透射。 本发明还提供了制造根据本发明的APSM的方法。

公开(公告)号：US06696224B2

公开(公告)日：2004-02-24

申请号：US10293164

申请日：2002-11-12

申请人： J. Brett Rolfson

发明人： J. Brett Rolfson

IPC分类号： G03F726

CPC分类号： H01L21/31133 ,  H01L21/0273

摘要： A method of masking and etching a semiconductor substrate includes forming a layer to be etched over a semiconductor substrate. An imaging layer is formed over the layer to be etched. Selected regions of the imaging layer are removed to leave a pattern of openings extending only partially into the imaging layer. After the removing, the layer to be etched is etched using the imaging layer as an etch mask. In one implementation, an ion implant lithography method of processing a semiconductor includes forming a layer to be etched over a semiconductor substrate. An imaging layer of a selected thickness is formed over the layer to be etched. Selected regions of the imaging layer are ion implanted to change solvent solubility of implanted regions versus non-implanted regions of the imaging layer, with the selected regions not extending entirely through the imaging layer thickness. The ion implanted regions of the imaging layer are removed to leave a pattern of openings extending only partially into the imaging layer. After the removing, the layer to be etched is etched using the imaging layer as an etch mask.

摘要翻译： 掩模和蚀刻半导体衬底的方法包括在半导体衬底上形成待蚀刻的层。 在待蚀刻的层上形成成像层。 去除成像层的选定区域以留下仅部分地延伸到成像层中的开口图案。 在去除之后，使用成像层作为蚀刻掩模蚀刻待蚀刻的层。 在一个实施方案中，处理半导体的离子注入光刻方法包括在半导体衬底上形成待蚀刻的层。 在待蚀刻层上形成所选厚度的成像层。 成像层的选定区域被离子注入以改变注入区域对成像层的非注入区域的溶剂溶解度，其中所选择的区域不完全延伸穿过成像层厚度。 去除成像层的离子注入区域以留下仅部分地延伸到成像层中的开口图案。 在去除之后，使用成像层作为蚀刻掩模蚀刻待蚀刻的层。

公开(公告)号：US06555432B2

公开(公告)日：2003-04-29

申请号：US09733820

申请日：2000-12-08

申请人： Gurtej S. Sandhu ,  J. Brett Rolfson

发明人： Gurtej S. Sandhu ,  J. Brett Rolfson

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L28/40 ,  H01L28/82 ,  H01L28/84 ,  H01L28/86 ,  H01L28/90

摘要： Disclosed is a capacitor construction for a more uniformly thick capacitor dielectric layer, and a method for fabricating the same. The method has special utility where the bottom electrode comprises composite layers over which the capacitor dielectric demonstrates differential growth during deposition. Exposed portions of an underlying first electrode layer, are covered either by a conductive or dielectric spacer, or by a dielectric padding. For the preferred embodiments, in which the bottom electrode comprises titanium carbonitride over rough polysilicon, a dielectric padding may be formed during a rapid thermal nitridation step, which causes silicon nitride to grow out of an exposed polysilicon sidewall. Alternatively, a sidewall spacer may be formed by deposition an additional layer of titanium nitride over the original titanim nitride strap, and performing a spacer etch.

公开(公告)号：US06506689B2

公开(公告)日：2003-01-14

申请号：US09804604

申请日：2001-03-12

申请人： J. Brett Rolfson

发明人： J. Brett Rolfson

IPC分类号： H01L21469

CPC分类号： H01L21/67051 ,  Y10S438/906

摘要： A method for removing contaminants from a semiconductor wafer having a spin on coating of material. Contaminants are removed by applying a cleaning solution to the periphery, and preferably, the exposed backside of the wafer after the edge bead has been dissolved and removed. The cleaning solution is formulated to react chemically with unwanted coating material residue to form a compound that may be ejected from the periphery of the spinning wafer. Any residual solution or precipitate that is not ejected from the wafer may be rinsed away with water, preferably deoinized water. One exemplary use of this method is the removal of metallic contaminants that may be left on the periphery and backside of a wafer after the formation of ferroelectric film coatings. A cleaning solution comprising a mixture of hydrochloric acid HCl and water H2O or,ammonium hydroxide NH4OH and water H2O is applied to the periphery of the spinning wafer. The cleaning solution will react with any residual metal ions to form a metal chloride or metal hydroxide that is ejected from the wafer along with the cleaning solution.

摘要翻译： 一种用于从具有材料旋涂的半导体晶片去除污染物的方法。 通过将清洁溶液施加到周边，并且优选地，在边缘珠被溶解并除去之后，暴露的晶片的背面去除污染物。 配制清洁溶液以与不想要的涂料残留物进行化学反应以形成可从旋转晶片周边喷出的化合物。 任何不会从晶片喷出的残余溶液或沉淀物可用水，优选脱水的水冲洗掉。 该方法的一个示例性用途是在形成铁电膜涂层之后去除可能留在晶片的周边和背面上的金属污染物。 将包含盐酸HCl和水H 2 O或氢氧化铵NH 4 OH和水H 2 O的混合物的清洁溶液施加到旋转晶片的周边。 清洁溶液将与任何残留的金属离子反应形成与清洁溶液一起从晶片喷出的金属氯化物或金属氢氧化物。

公开(公告)号：US06482693B1

公开(公告)日：2002-11-19

申请号：US09452725

申请日：1999-11-30

申请人： J. Brett Rolfson ,  Monte Manning

发明人： J. Brett Rolfson ,  Monte Manning

IPC分类号： H01L218234

CPC分类号： H01L28/20 ,  H01L21/76888 ,  H01L21/76895 ,  H01L27/11 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904 ,  Y10S438/98

摘要： Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

摘要翻译： 公开了从半导体材料形成电阻器和二极管的方法，以及结合电阻器的静态随机存取存储器（SRAM）单元以及并入电阻器和二极管的集成电路的方法。 提供要进行电连接的节点。 在节点外部设置一个电绝缘层。 在节点上的电绝缘层中设置开口。 开口填充有半导体材料，其取决于配置用作垂直细长的二极管和电阻器中的一个或两个。

公开(公告)号：US06452678B2

公开(公告)日：2002-09-17

申请号：US09928286

申请日：2001-08-10

申请人： Randhir P. S. Thakur ,  Michael Nuttall ,  J. Brett Rolfson ,  Robert James Burke

发明人： Randhir P. S. Thakur ,  Michael Nuttall ,  J. Brett Rolfson ,  Robert James Burke

IPC分类号： G01B1100

CPC分类号： G01B11/303

摘要： Disclosed is a process for analyzing the surface characteristics of opaque materials. The method comprises in one embodiment the use of a UV reflectometer to build a calibration matrix of data from a set of control samples and correlating a desired surface characteristic such as rouglness or surface area to the set of reflectances of the control samples. The UV reflectometer is then used to measure the reflectances of a test sample of unknown surface characteristics. Reflectances are taken at a variety of angles of reflection for a variety of wavelengths, preferably between about 250 nanometers to about 400 nanometers. These reflectances are then compared against the reflectances of the calibration matrix in order to correlate the closest data in the calibration matrix. By so doing, a variety of information is thereby concluded, due to the broad spectrum of wavelengths and angles of reflection used. This includes information pertaining to the roughness and surface area, as well as other surface characteristics such as grain size, grain density, grain shape, and boundary size between the grains. Surface characteristic evaluation can be conducted in-process in a manner which is non-destructive to the test sample. The method is particularly useful for determining the capacitance of highly granular polysilicon test samples used in the construction of capacitator plates in integrated circuit technology, and can be used to determine the existence of flat smooth surfaces, and the presence of prismatic and hemispherical irregularities on flat smooth surfaces.

摘要翻译： 公开了一种用于分析不透明材料的表面特性的方法。 该方法在一个实施例中包括使用UV反射计来构建来自一组控制样本的数据的校准矩阵，并将期望的表面特性（例如粗糙度或表面积）与对照样品的一组反射率相关联。 然后使用UV反射计来测量未知表面特性的测试样品的反射率。 对于各种波长，优选在约250纳米到约400纳米之间的各种反射角拍摄反射率。 然后将这些反射率与校准矩阵的反射率进行比较，以便将校准矩阵中最接近的数据相关联。 通过这样做，由于广泛的波长和使用的反射角度，从而得出各种信息。 这包括关于粗糙度和表面积的信息，以及晶粒之间的其他表面特性，例如晶粒尺寸，晶粒密度，晶粒形状和边界尺寸。 表面特性评估可以以对测试样品非破坏性的方式进行。 该方法对于确定集成电路技术中电容器板结构中使用的高度粒状多晶硅测试样品的电容特别有用，可用于确定平坦光滑表面的存在，以及平面上存在棱镜和半球形不规则 光滑的表面。

公开(公告)号：US06391734B1

公开(公告)日：2002-05-21

申请号：US09470332

申请日：1999-12-22

申请人： J. Brett Rolfson ,  Monte Manning

发明人： J. Brett Rolfson ,  Monte Manning

IPC分类号： H01L2120

CPC分类号： H01L28/20 ,  H01L21/76888 ,  H01L21/76895 ,  H01L27/11 ,  H01L27/1112

摘要： Disclosed are methods of forming resistors and diodes from semiconductive material, and static random access memory (SRAM) cells incorporating resistors, and to integrated circuitry incorporating resistors and diodes. A node to which electrical connection is to be made is provided. An electrically insulative layer is provided outwardly of the node. An opening is provided in the electrically insulative layer over the node. The opening is filled with semiconductive material which depending on configuration serves as one or both of a vertically elongated diode and resistor.

公开(公告)号：US06342435B1

公开(公告)日：2002-01-29

申请号：US09441925

申请日：1999-11-17

申请人： J. Brett Rolfson ,  Tyler A. Lowrey ,  Fernando Gonzalez ,  W. Richard Barbour

发明人： J. Brett Rolfson ,  Tyler A. Lowrey ,  Fernando Gonzalez ,  W. Richard Barbour

IPC分类号： H01L21324

CPC分类号： H01L21/823892 ,  H01L21/2253

摘要： Disclosed is an improved CMOS fabrication method that allows an implanted well in a bare silicon wafer to be simultaneously, driven annealed and denuded in a single process step. More specifically, a single step drive-anneal-denude (DAD) process is accomplished using a non-inert ambient environment. The DAD process is accomplished in a combination argon/hydrogen ambient environment. This process causes the silicon wafer to roughen slightly and is followed by an oxidation step, that optionally takes place in a combination argon/oxygen ambient environment to smooth out the silicon surface. The oxidation step may also optionally act as a pad-oxide or screening oxide for subsequent fabrication.

摘要翻译： 公开了一种改进的CMOS制造方法，其允许在单个工艺步骤中同时，驱动退火和剥离裸硅晶片中的注入阱。 更具体地，使用非惰性环境环境来实现单级驱动退火 - 脱模（DAD）工艺。 DAD过程在氩/氢环境的组合环境中完成。 该方法使得硅晶片稍微粗糙化，随后进行氧化步骤，其可选地在氩气/氧气环境环境中进行，以平滑硅表面。 氧化步骤还可以任选地用作氧化垫或筛选氧化物用于随后的制造。