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    Memory system having point-to-point (PTP) and point-to-two-point (PTTP) links between devices
    31.
    发明授权
    Memory system having point-to-point (PTP) and point-to-two-point (PTTP) links between devices 有权
    在设备之间具有点到点（PTP）和点到两点（PTTP）链路的存储器系统

    公开(公告)号：US07405949B2

    公开(公告)日：2008-07-29

    申请号：US11603648

    申请日：2006-11-22

    Applicant: Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

    Inventor： Jae-Jun Lee ,  Joo-Sun Choi ,  Kyu-Hyoun Kim ,  Kwang-Soo Park

    IPC: H05K7/14

    CPC classification number: G11C5/063

    Abstract: A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.

    Abstract translation: 存储器系统具有第一和第二主存储器以及分别耦合到第一和第二主存储器的第一和第二辅助存储器，耦合器包括至少一个点到点连接。 存储器模块包括第一和第二主要和第一和第二辅助存储器中的至少两个。 诸如连接器或焊料的第一连接元件将存储器模块连接到母板。 诸如连接器或焊料的第二连接元件将第一和第二初级和第二和第二辅助存储器中的至少一个连接到母板。 第一存储器模块上的至少一个存储器耦合到至少一个其他存储器。 存储器系统还包括存储器控制器，其通过点对二点链接连接到主存储器。

    SEMICONDUCTOR MEMORY DEVICE WITH DATA BUS SCHEME FOR REDUCING HIGH FREQUENCY NOISE
    32.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE WITH DATA BUS SCHEME FOR REDUCING HIGH FREQUENCY NOISE 审中-公开
    具有数据总线方案的半导体存储器件，用于降低高频噪声

    公开(公告)号：US20080030286A1

    公开(公告)日：2008-02-07

    申请号：US11755791

    申请日：2007-05-31

    Applicant: Myun-Joo Park ,  Jae-jun LEE

    Inventor： Myun-Joo Park ,  Jae-jun LEE

    IPC: H01P5/12

    CPC classification number: H05K1/0216 ,  G11C7/1006 ,  H05K1/0237 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/09727 ,  H05K2201/09781

    Abstract: A semiconductor memory device includes memory modules which have memories and a data bus which transfers data to the memory modules, in which the data bus comprises a low frequency band data pass unit which removes the high frequency component of the data and sends the data to the memory modules. The low frequency band data pass unit comprises a plurality of stubs which are connected to the data bus in parallel and are formed as printed circuit board (PCB) patterns. The low frequency band data pass unit comprises a plurality of plates that are connected to the data bus in parallel and are formed as PCB patterns. The low frequency band data pass unit has a shape in which parts having a wide width and parts having a narrow width are alternately connected. Therefore, without adding a separate passive device, the semiconductor memory device reduces the high frequency noise of data transferred through a data bus such that the voltage margin of the data improves, the cost for passive devices such as capacitors, is reduced, and the process for attaching the passive devices is simplified.

    Abstract translation: 半导体存储器件包括具有存储器的存储器模块和将数据传送到存储器模块的数据总线，其中数据总线包括一个低频带数据传递单元，该单元去除数据的高频分量并将数据发送到 内存模块 低频带数据传送单元包括并联连接到数据总线并形成为印刷电路板（PCB）图案的多个短截线。 低频带数据传送单元包括并联连接到数据总线并形成为PCB图案的多个板。 低频带数据传送单元具有宽度宽的部分和宽度窄的部分交替连接的形状。 因此，在不添加单独的无源器件的情况下，半导体存储器件减少通过数据总线传送的数据的高频噪声，从而数据的电压裕度提高，诸如电容器等无源器件的成本降低，并且该过程 用于安装无源器件简化了。

    Memory system capable of changing configuration of memory modules
    33.
    发明申请
    Memory system capable of changing configuration of memory modules 有权
    能够更改内存模块配置的内存系统

    公开(公告)号：US20070161264A1

    公开(公告)日：2007-07-12

    申请号：US11649266

    申请日：2007-01-04

    Applicant: Jae-jun Lee ,  Jong-hoon Kim ,  Kwang-soo Park

    Inventor： Jae-jun Lee ,  Jong-hoon Kim ,  Kwang-soo Park

    IPC: H01R12/00

    CPC classification number: G06F13/1694

    Abstract: A memory system is disclosed with first, second, and third connectors located on a system board, the third connector including pins connected to the pins of the first and second connectors through channels, and a memory controller connected to the pins of the third connector through channels. The memory system, as configured in a first memory capacity, comprises; dummy memory modules and a first memory module connected to the memory controller by installing the dummy memory modules in the first and second connectors and installing the first memory module in the third connector. The memory system, as alternately configured in a second memory capacity larger than the first memory capacity, comprises second memory modules connected to the memory controller by installing the second memory modules in only the first and second connectors.

    Abstract translation: 公开了一种存储系统，其中位于系统板上的第一，第二和第三连接器，第三连接器包括通过通道连接到第一和第二连接器的引脚的引脚，以及连接到第三连接器的引脚的存储器控​​制器，通过 频道 如第一存储器容量中配置的存储器系统包括： 虚拟存储器模块和通过将虚拟存储器模块安装在第一和第二连接器中而连接到存储器控制器的第一存储器模块，并将第一存储器模块安装在第三连接器中。 交替地配置在大于第一存储器容量的第二存储器容量中的存储器系统包括通过仅将第二存储器模块安装在第一和第二连接器中而连接到存储器控制器的第二存储器模块。

    Impedance adjustment circuits and methods using replicas of variable impedance circuits
    35.
    发明申请
    Impedance adjustment circuits and methods using replicas of variable impedance circuits 失效
    阻抗调节电路和使用可变阻抗电路的副本的方法

    公开(公告)号：US20060087339A1

    公开(公告)日：2006-04-27

    申请号：US11247846

    申请日：2005-10-11

    Applicant: Hoe-ju Chung ,  Jae-jun Lee ,  Kyu-hyoung Kim

    Inventor： Hoe-ju Chung ,  Jae-jun Lee ,  Kyu-hyoung Kim

    IPC: H03K19/003

    CPC classification number: H04L25/0278

    Abstract: An impedance adjustment circuit for controlling an impedance of a variable impedance circuit includes a calibration circuit including a replica of the variable impedance circuit and configured to generate an impedance control signal for the variable impedance circuit based on a voltage generated at the replica of the variable impedance circuit in response to a reference current. The calibration circuit may be configured to generate the reference current based on a reference resistor coupled thereto. In particular, the calibration circuit may be configured to match a current in the replica of the variable impedance circuit and a current in the reference resistor to generate the voltage at the replica of the variable impedance circuit.

    Abstract translation: 用于控制可变阻抗电路的阻抗的阻抗调节电路包括：校准电路，包括可变阻抗电路的副本，并且被配置为基于在可变阻抗的复制品处产生的电压产生用于可变阻抗电路的阻抗控制信号 电路响应于参考电流。 校准电路可以被配置为基于与其耦合的参考电阻产生参考电流。 特别地，校准电路可以被配置为使可变阻抗电路的副本中的电流与参考电阻中的电流相匹配，以在可变阻抗电路的复制品处产生电压。

    Organometal-containing norbornene monomer, photoresist containing its polymer, manufacturing method thereof, and method of forming photoresist patterns
    36.
    发明授权
    Organometal-containing norbornene monomer, photoresist containing its polymer, manufacturing method thereof, and method of forming photoresist patterns 失效
    含有机金属的降冰片烯单体，含有其聚合物的光致抗蚀剂，其制造方法和形成光致抗蚀剂图案的方法

    公开(公告)号：US06607867B1

    公开(公告)日：2003-08-19

    申请号：US09790632

    申请日：2001-02-23

    Applicant: Jin-Baek Kim ,  Jae-Jun Lee ,  Jae-Sung Kang

    Inventor： Jin-Baek Kim ,  Jae-Jun Lee ,  Jae-Sung Kang

    IPC: G03F7004

    CPC classification number: G03F7/0395 ,  C07F7/081 ,  G03F7/0045 ,  G03F7/0758 ,  Y10S430/106

    Abstract: The present invention relates to norbornene monomers with a novel functional group containing an organometal as shown in the following Formula (I) or (II), a photoresist containing its polymers, manufacturing method thereof, and a method of forming photoresist patterns. Unlike existing polymers for photoresist matrix, polymers made by norbornene monomers described in the present invention is a chemical amplification type induced by photosensitive acids and can result in difference in silicon content between the exposed area and unexposed area due to dissociation of side chain containing silicon. The difference in the silicon content results in different etch rate with respect to oxygen plasma which makes dry developing possible.

    Abstract translation: 本发明涉及具有如下式（I）或（II）所示的含有有机金属的新型官能团的降冰片烯单体，含有其聚合物的光致抗蚀剂，其制造方法和形成光致抗蚀剂图案的方法。不存在聚合物 对于光致抗蚀剂基质，由本发明中描述的降冰片烯单体制成的聚合物是由光敏酸诱导的化学放大型，并且由于含有侧链的解离导致曝光区域与未曝光区域之间的硅含量差异。 硅含量的差异导致相对于氧等离子体的不同蚀刻速率，这使得干式显影成为可能。

    Reciprocating linear razor
    38.
    发明授权
    Reciprocating linear razor 有权
    往复线性剃须刀

    公开(公告)号：US09440365B2

    公开(公告)日：2016-09-13

    申请号：US13821264

    申请日：2011-09-16

    Applicant: Young Ho Park ,  Jae Jun Lee

    Inventor： Young Ho Park ,  Jae Jun Lee

    IPC: B26B21/38 ,  B26B21/40 ,  B26B21/52 ,  B26B21/36

    CPC classification number: B26B21/38 ,  B26B21/36 ,  B26B21/40 ,  B26B21/52

    Abstract: The present invention pertains to a razor, which includes: a gripping section combined with a housing; a head section coupled at one side of the housing; a razor blade cartridge mounted at a front surface of an upper end of the head section; and an eccentric cam module, which moves the razor blade cartridge to reciprocate in a cutting direction.

    Abstract translation: 本发明涉及一种剃刀，其包括：与壳体组合的抓握部分; 头部，其联接在所述壳体的一侧; 安装在所述头部的上端的前表面的剃刀刀片盒; 以及偏心凸轮模块，其使剃刀刀片盒沿切割方向往复运动。

    Apparatus and method for inputting writing information according to writing pattern
    39.
    发明授权
    Apparatus and method for inputting writing information according to writing pattern 有权
    根据书写模式输入写入信息的装置和方法

    公开(公告)号：US08952906B2

    公开(公告)日：2015-02-10

    申请号：US13386249

    申请日：2009-07-31

    Applicant: Jae Jun Lee

    Inventor： Jae Jun Lee

    IPC: G06F3/041 ,  G06F3/043 ,  G06F3/0488

    CPC classification number: G06F3/043 ,  G06F3/0488

    Abstract: Provided are a method and apparatus for inputting handwriting in a digital electronic apparatus. Various patterns defining methods of generating pressure information according to handwriting input are stored in advance, and a user selects a pattern similar to a pattern of the user or selects a desired handwriting pattern to perform the handwriting, so that pressure information is generated according to the handwriting pattern and the handwriting is displaying with a thickness corresponding to the pressure information. Therefore, it is possible to solve a problem of monotonous handwriting input in the related art where only the position is input and the handwriting is output with the same thickness.

    Abstract translation: 提供了一种用于在数字电子设备中输入笔迹的方法和装置。 预先存储定义根据手写输入产生压力信息的方法的各种模式，并且用户选择与用户的图案相似的图案或选择所需的手写图案来执行手写，从而根据 手写图案和手写显示具有与压力信息对应的厚度。 因此，可以解决现有技术中仅输入位置并以相同厚度输出笔迹的单调手写输入的问题。

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