公开(公告)号：US20080316819A1

公开(公告)日：2008-12-25

申请号：US12199834

申请日：2008-08-28

申请人： Jin-Yub LEE

发明人： Jin-Yub LEE

IPC分类号： G11C16/04 ,  G11C8/00

CPC分类号： G11C11/5621 ,  G11C16/0483 ,  G11C2211/5641

摘要： There is provided a flash memory device capable of manipulating multi-bit and single-bit data. The flash memory device can include a memory cell array with a plurality of memory blocks. The flash memory device can also include a judgment circuit for storing multi-bit/single-bit information indicating whether each of the memory blocks is a multi-bit memory block or not, determining whether or not a memory block of an inputted block address is a multi-bit memory block according to the stored multi-bit/single-bit information and outputting an appropriate flag signal. A read/write circuit for selectively performing multi-bit and single-bit read/program operations of the memory block corresponding to the block address is also included, as well as control logic for controlling the read/write circuit such that the read/write circuit can perform multi-bit or single-bit read/program operations based on the flag signal. An error checking and correction (ECC) circuit including a multi-bit ECC unit and a single-bit ECC unit for checking and correcting an error in a data of the read/write circuit can also be included.

摘要翻译： 提供了能够操纵多位和单位数据的闪速存储器件。 闪存器件可以包括具有多个存储器块的存储单元阵列。 闪存装置还可以包括用于存储指示每个存储块是否是多位存储块的多位/单位信息的判断电路，确定输入块地址的存储块是否为 根据所存储的多位/单位信息的多位存储器块，并输出适当的标志信号。 还包括用于选择性地执行与块地址相对应的存储块的多位和单位读/写操作的读/写电路，以及用于控制读/写电路的控制逻辑，使得读/写 电路可以基于标志信号执行多位或单位读/写操作。 还可以包括包括用于检查和校正读/写电路的数据中的错误的多位ECC单元和单位ECC单元的错误检查和校正（ECC）电路。

公开(公告)号：US07453713B2

公开(公告)日：2008-11-18

申请号：US11700839

申请日：2007-02-01

申请人： Hyung-Min Kim ,  Sang-Chul Kang ,  Jin-Yub Lee

发明人： Hyung-Min Kim ,  Sang-Chul Kang ,  Jin-Yub Lee

IPC分类号： G11C5/06

CPC分类号： G11C8/12 ,  G11C16/10 ,  H01L25/065 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is directed to a dual chip package that is connected to a host and includes a first memory chip and a second memory chip. Each of the first and second memory chips includes a flash memory; an option pad connected to either a first or second voltage; a register configured to store a flag signal indicating whether a memory chip is selected; a comparator circuit configured to compare a flag signal stored in the register with a logic value apparent at the option pad to generate a flash access signal. Each of the first and second memory chips also includes a memory controller unit configured to access the flash memory in response to the flash access signal, and an interrupt controller unit configured to provide an interrupt signal to the host in response to the flash access signal and a control signal provided from the host.

摘要翻译： 本发明涉及连接到主机并且包括第一存储器芯片和第二存储器芯片的双芯片封装。 第一和第二存储器芯片中的每一个包括闪速存储器; 连接到第一或第二电压的选项焊盘; 寄存器，被配置为存储指示是否选择存储器芯片的标志信号; 比较器电路，被配置为将存储在所述寄存器中的标志信号与在所述选项焊盘处显现的逻辑值进行比较以产生闪存存取信号。 第一和第二存储器芯片中的每一个还包括被配置为响应于闪存访问信号访问闪速存储器的存储器控​​制器单元和被配置为响应于闪存访问信号向主机提供中断信号的中断控制器单元，以及 从主机提供的控制信号。

公开(公告)号：US20080224752A1

公开(公告)日：2008-09-18

申请号：US12045125

申请日：2008-03-10

申请人： Chul-Ho LEE ,  Jin-Yub LEE

发明人： Chul-Ho LEE ,  Jin-Yub LEE

IPC分类号： G06F1/04

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3275 ,  Y02D10/126 ,  Y02D10/14

摘要： An internal clock generator, system and method of generating the internal clock are disclosed. The method comprises detecting the level of an operating voltage within the system, comparing the level of the operating voltage to a target voltage level and generating a corresponding detection signal, and selecting between a normal clock and an alternate clock having a period longer than the period of the normal clock in relation to the detection signal and generating an internal clock on the basis of the selection.

摘要翻译： 公开了一种产生内部时钟的内部时钟发生器，系统和方法。 该方法包括检测系统内的工作电压的电平，将工作电压的电平与目标电压电平进行比较，并产生相应的检测信号，以及选择正常时钟和具有比周期长的周期的备用时钟 的相对于检测信号的正常时钟，并且基于该选择产生内部时钟。

公开(公告)号：US20080204064A1

公开(公告)日：2008-08-28

申请号：US12034878

申请日：2008-02-21

申请人： Pyung-Moon Zhang ,  Jin-Yub Lee

发明人： Pyung-Moon Zhang ,  Jin-Yub Lee

IPC分类号： G01R31/26

CPC分类号： G01R31/3004 ,  G11C29/02 ,  G11C29/021 ,  G11C29/1201 ,  G11C29/48 ,  G11C29/56

摘要： Provided are a test system and a related high voltage measurement method. The method includes applying an external voltage signal to one or more of a plurality of DUTs via the shared channel, comparing the external voltage signal with a high voltage signal internally generated by the one or more DUTs and generating a corresponding comparison result, and determining a voltage level for each respective high voltage signal in accordance with the comparison result.

摘要翻译： 提供了一种测试系统和相关的高电压测量方法。 该方法包括：经由共享信道将外部电压信号施加到多个DUT中的一个或多个，将外部电压信号与由一个或多个DUT内部产生的高电压信号进行比较并产生相应的比较结果， 根据比较结果对各高压信号进行电压电平。

公开(公告)号：US20080084768A1

公开(公告)日：2008-04-10

申请号：US11604692

申请日：2006-11-28

申请人： Dae-sik Park ,  Jin-yub Lee

发明人： Dae-sik Park ,  Jin-yub Lee

IPC分类号： G11C16/04 ,  G11C7/10 ,  G11C11/34

CPC分类号： G11C7/1078 ,  G11C7/1087 ,  G11C11/5628

摘要： A memory device and method thereof are provided. The example memory device may include a first buffer receiving most significant bit (MSB) data and least significant bit (LSB) data to be stored within a memory cell, a second buffer loading stored LSB data stored from the memory cell and a data loader generating at least one load signal based upon logic levels of the received MSB data from the first buffer and the loaded LSB data from the memory cell, the at least one load signal controlling programming permissions for the memory cell. The example method may include receiving LSB data, storing the received LSB data within a memory cell, receiving MSB data, loading the LSB data from the programmed memory cell, generating at least one load signal based upon logic levels of the received MSB data and the loaded LSB data, the at least one load signal controlling programming permissions for the memory cell and storing the MSB data within the memory cell based on the at least one load signal.

摘要翻译： 提供了一种存储器件及其方法。 该示例性存储器件可以包括接收要存储在存储器单元内的最高有效位（MSB）数据和最低有效位（LSB））数据的第一缓冲器，第二缓冲器加载从存储器单元存储的存储的LSB数据，以及数据加载器生成 基于来自第一缓冲器的接收到的MSB数据的逻辑电平和来自存储器单元的加载的LSB数据的至少一个负载信号，所述至少一个负载信号控制对存储器单元的编程许可。 示例性方法可以包括接收LSB数据，将接收的LSB数据存储在存储器单元内，接收MSB数据，从编程的存储器单元加载LSB数据，基于所接收的MSB数据的逻辑电平产生至少一个负载信号，以及 所述至少一个负载信号控制所述存储器单元的编程许可，并且基于所述至少一个负载信号将所述MSB数据存储在所述存储器单元内。

公开(公告)号：US20080055997A1

公开(公告)日：2008-03-06

申请号：US11842995

申请日：2007-08-22

申请人： Jin-Yub Lee

发明人： Jin-Yub Lee

IPC分类号： G11C16/00

CPC分类号： G11C16/349 ,  G11C16/3495

摘要： A flash memory device is disclosed and includes a memory cell array comprising memory cells arranged in rows and columns, a page buffer circuit having a single latch structure and configured to read data from a selected page in the memory cell array, and a controller controlling the page buffer circuit to detect memory cells having an improper voltage distribution causes by charge leakage within the selected page.

摘要翻译： 公开了一种闪速存储器件，包括存储单元阵列，其包括以行和列排列的存储单元，具有单个锁存结构并被配置为从存储单元阵列中的选定页读取数据的页缓冲器电路，以及控制器 用于检测具有不正确的电压分布的存储单元的页缓冲电路是由选定页内的电荷泄漏引起的。

公开(公告)号：US07324378B2

公开(公告)日：2008-01-29

申请号：US11322893

申请日：2005-12-29

申请人： Jin-Yub Lee

发明人： Jin-Yub Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C16/0483

摘要： In an embodiment, a method of driving a program operation in a nonvolatile semiconductor memory device is operable without discharging a bitline connected to a memory cell to be programmed between a program period and a verifying period. This remarkably improves programming speed and reduces current consumption.

摘要翻译： 在一个实施例中，一种在非易失性半导体存储器件中驱动编程操作的方法可操作，而不会在连接到要在编程周期和验证周期之间编程的存储器单元的位线放电。 这显着提高了编程速度并降低了电流消耗。

公开(公告)号：US20070183221A1

公开(公告)日：2007-08-09

申请号：US11567895

申请日：2006-12-07

申请人： DAE-SIK PARK ,  Jin-Yub Lee

发明人： DAE-SIK PARK ,  Jin-Yub Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/30 ,  G11C16/16

摘要： An erase voltage generation circuit providing a uniform erase execution time and a non-volatile semiconductor memory device having the same, in which the erase voltage generation circuit includes a high voltage generation unit, a voltage level detection unit, an execution time checking unit and a discharging unit. The high voltage generation unit generates an erase voltage. The voltage level detection unit detects the erase voltage and generates a level detection signal. The level detection signal is activated when the erase voltage reaches a target voltage. The execution time checking unit generates an execution end signal that is activated in response to the lapse of an erase execution time from the activation of the level detection signal. The discharging unit discharges the erase voltage as a discharge voltage. The high voltage generation unit is disabled in response to the activation of the execution end signal, and the discharging unit is enabled in response to the activation of the execution end signal.

摘要翻译： 提供均匀擦除执行时间的擦除电压产生电路和具有该擦除执行时间的非易失性半导体存储器件，其中擦除电压产生电路包括高电压产生单元，电压电平检测单元，执行时间检查单元和 放电单元 高电压产生单元产生擦除电压。 电压电平检测单元检测擦除电压并产生电平检测信号。 当擦除电压达到目标电压时，电平检测信号被激活。 执行时间检查单元生成响应于从电平检测信号的激活而经过擦除执行时间而被激活的执行结束信号。 放电单元将擦除电压作为放电电压放电。 响应于执行结束信号的激活，高电压生成单元被禁用，并且放电单元响应于执行结束信号的激活而被使能。

公开(公告)号：US20070147164A1

公开(公告)日：2007-06-28

申请号：US11484176

申请日：2006-07-11

申请人： Jong-Hoon Lee ,  Jin-Yub Lee ,  Sang-Won Hwang

发明人： Jong-Hoon Lee ,  Jin-Yub Lee ,  Sang-Won Hwang

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C8/12

摘要： A row decoder preventing leakage current and a semiconductor memory device including the same are provided. The row decoder includes an address decoder and a selection signal generator. The address decoder decodes a predetermined address signal and activates an enable signal. The selection signal generator electrically connects a boosted voltage node to an output node to activate a block selection signal when the enable signal is activated and electrically breaks a path between the boosted voltage node and the output node and a path between the boosted voltage node and a ground voltage node when the enable signal is deactivated. The selection signal generator includes a feedback circuit, a switch, and a direct current (DC) path breaker. The feedback circuit is electrically connected to the output node to generate an output voltage that varies with a voltage level of the block selection signal. The switch transmits the output voltage of the feedback circuit to the output node. The DC path breaker turns on the switch when the enable signal is activated and turns off the switch when the enable signal is deactivated. Accordingly, when a supply voltage applied to the semiconductor memory device is low, a DC path is broken in the row decoder, thereby preventing the leakage current.

摘要翻译： 提供了防止泄漏电流的行解码器和包括其的半导体存储器件。 行解码器包括地址解码器和选择信号发生器。 地址解码器解码预定的地址信号并激活使能信号。 选择信号发生器将升压电压节点电连接到输出节点，以在使能信号被激活并且电断开升压的电压节点和输出节点之间的路径时，激活块选择信号，以及升压电压节点和 当使能信号被禁用时，接地电压节点。 选择信号发生器包括反馈电路，开关和直流（DC）路径断路器。 反馈电路电连接到输出节点以产生随块选择信号的电压电平而变化的输出电压。 开关将反馈电路的输出电压传输到输出节点。 当使能信号被激活时，直流通路断路器接通开关，当使能信号被禁用时，断开开关。 因此，当施加到半导体存储器件的电源电压低时，行解码器中的DC路径被破坏，从而防止漏电流。

公开(公告)号：US07224624B2

公开(公告)日：2007-05-29

申请号：US11133214

申请日：2005-05-20

申请人： Jin-Yub Lee ,  Yong-Taek Jeong

发明人： Jin-Yub Lee ,  Yong-Taek Jeong

IPC分类号： G11C7/10 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C2216/14

摘要： Disclosed is a page buffer for a nonvolatile semiconductor memory device and a related method of operation. The page buffer includes a unidirectional driver between a loading latch unit used for storing a data bit in the page buffer and a bitline used to program a memory cell connected to the page buffer.

摘要翻译： 公开了一种用于非易失性半导体存储器件的页面缓冲器和相关的操作方法。 页缓冲器包括用于存储页缓冲器中的数据位的加载锁存单元与用于对连接到页缓冲器的存储单元进行编程的位线之间的单向驱动器。