公开(公告)号：US20180285158A1

公开(公告)日：2018-10-04

申请号：US15477026

申请日：2017-04-01

Applicant: Abhishek R. Appu ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

Inventor： Abhishek R. Appu ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

IPC: G06F9/50 ,  G06T1/60 ,  G06T1/20 ,  G06T15/00 ,  G06F9/48 ,  G06F1/32

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180032431A1

公开(公告)日：2018-02-01

申请号：US15219997

申请日：2016-07-26

Applicant: Joydeep Ray ,  James A. Valerio ,  Abhishek R. Appu

Inventor： Joydeep Ray ,  James A. Valerio ,  Abhishek R. Appu

IPC: G06F12/06 ,  G06F9/38

CPC classification number: G06F12/0646 ,  G06F9/34 ,  G06F9/3824 ,  G06F9/3887

Abstract: A graphics processor may be assigned a number of banks in a shared local memory to reduce the number of bank conflicts. In some cases, the number of banks may be higher than the single instruction multiple data slot number times the number of messages per cycle. The actual number of banks may be set to the next higher relatively prime number of 2n and 3 where n is 0-5.

公开(公告)号：US20150178203A1

公开(公告)日：2015-06-25

申请号：US14140256

申请日：2013-12-24

Applicant: Marc Torrant ,  Jorge E. Parra ,  Blaise Fanning ,  Joydeep Ray

Inventor： Marc Torrant ,  Jorge E. Parra ,  Blaise Fanning ,  Joydeep Ray

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/123

Abstract: Systems and methods for write allocation by a two-level memory controller. An example processing system comprises: a processing core; a memory controller communicatively coupled to the processing core; and a system memory communicatively coupled to the memory controller, the system memory comprising a first level memory and a second level memory; wherein the memory controller is configured, responsive to determining that a memory block referenced by a memory write request is not present in the first level memory, to allocate a new first level memory block without retrieving the memory block referenced by the request from the second level memory, wherein the memory write request is represented by an overwrite type memory write request.

Abstract translation: 由两级内存控制器进行写入分配的系统和方法。 一个示例处理系统包括：处理核心; 通信地耦合到所述处理核心的存储器控​​制器; 以及系统存储器，其通信地耦合到所述存储器控制器，所述系统存储器包括第一级存储器和第二级存储器; 其中，所述存储器控制器被配置为响应于确定由所述存储器写请求引用的存储器块不存在于所述第一级存储器中，以分配新的第一级存储器块而不从所述第二级检索由所述请求引用的所述存储器块 存储器，其中存储器写入请求由覆盖型存储器写入请求表示。

公开(公告)号：US20150082002A1

公开(公告)日：2015-03-19

申请号：US14031398

申请日：2013-09-19

Applicant: Jorge E. Parra ,  Joydeep Ray ,  Ramadass Nagarajan

Inventor： Jorge E. Parra ,  Joydeep Ray ,  Ramadass Nagarajan

IPC: G06F12/10

CPC classification number: H04L9/3242 ,  G06F12/0607 ,  G06F13/16

Abstract: Dynamic heterogeneous hashing function technology for balancing memory requests between multiple memory channels is described. A processor includes functional units and multiple memory channels, and a memory controller unit (MCU) coupled between them. The MCU includes a dynamic heterogeneous hashing module (DHHM) that includes multiple specific-purpose hashing function blocks that define different interleaving sequences for memory requests to alternately access the multiple memory channels. The DHHM also includes a hashing-function selection block. The hashing-function selection block is operable to identify a requesting functional unit originating a current memory request and to select one of the specific-purpose hashing function blocks for the current memory request in view of the requesting functional unit.

Abstract translation: 描述了用于平衡多个存储器通道之间的存储器请求的动态异构散列函数技术。 处理器包括功能单元和多个存储器通道，以及耦合在它们之间的存储器控​​制器单元（MCU）。 MCU包括动态异构散列模块（DHHM），其包括多个特定目的散列功能块，其定义用于交替访问多个存储器通道的存储器请求的不同交错序列。 DHHM还包括散列函数选择块。 散列函数选择块可用于识别发起当前存储器请求的请求功能单元，并根据请求功能单元选择当前存储器请求的特定目的散列功能块之一。