公开(公告)号：US20110039359A1

公开(公告)日：2011-02-17

申请号：US12923949

申请日：2010-10-15

Applicant: Isao Takasu ,  Yuko Nomura ,  Tsuyoshi Hioki ,  Isao Amemiya ,  Kazuhide Abe

Inventor： Isao Takasu ,  Yuko Nomura ,  Tsuyoshi Hioki ,  Isao Amemiya ,  Kazuhide Abe

IPC: H01L33/48

CPC classification number: H01L33/54 ,  H01L33/46 ,  H01L33/507 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2933/0041 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of manufacturing a light emitting device. The method includes: mounting a light emitting chip on a substrate; forming a transparent resin portion and a phosphor layer by using a liquid droplet discharging apparatus, the transparent resin portion being formed in a shape of a dome and covering the light emitting chip to fill an exterior thereof on the substrate, a phosphor layer containing phosphor and being formed on an exterior of the transparent resin portion close to at least a top side thereof; and forming a reflecting layer at a position exterior of the transparent resin portion and the phosphor layer close to the substrate.

Abstract translation: 一种制造发光器件的方法。 该方法包括：将发光芯片安装在基板上; 通过使用液滴喷射装置形成透明树脂部分和荧光体层，所述透明树脂部分形成为圆顶形状并且覆盖所述发光芯片以将其外部填充在所述基板上，所述荧光体层包含磷光体和 形成在透明树脂部分的至少其顶侧附近的外部; 并且在透明树脂部分的外部和靠近基板的荧光体层的位置处形成反射层。

公开(公告)号：US07769352B2

公开(公告)日：2010-08-03

申请号：US11568365

申请日：2006-09-25

Applicant: Takashi Kawakubo ,  Toshihiko Nagano ,  Kazuhide Abe ,  Michihiko Nishigaki

Inventor： Takashi Kawakubo ,  Toshihiko Nagano ,  Kazuhide Abe ,  Michihiko Nishigaki

IPC: H04B1/40 ,  H04B7/00 ,  H04L27/22

CPC classification number: H04L27/2272 ,  H03C3/0966 ,  H03D3/242 ,  H04B1/38 ,  H04L27/2273 ,  H04L2027/0016 ,  H04L2027/0022 ,  H04L2027/0055 ,  H04W56/00 ,  H04W88/02 ,  Y02D70/1222 ,  Y02D70/40

Abstract: A receiver has a first voltage control oscillator configured to generate a first oscillation signal, a second voltage control oscillator configured to generate a second oscillation signal having a first phase, a first phase comparator configured to detect a phase difference between the first and second oscillation signals, a demodulator configured to perform demodulation processing of the received signal and to generate timing information of a second phase included in the first oscillation signal, a second phase comparator configured to detect the phase difference between the first and second oscillation signals, and a first control voltage generator configured to generate a first control voltage for controlling a phase and a frequency of the second voltage control oscillator based on the phase difference detected by the second phase comparator.

Abstract translation: 一种接收器具有：第一电压控制振荡器，被配置为产生第一振荡信号;第二压控振荡器，被配置为产生具有第一相位的第二振荡信号;第一相位比较器，被配置为检测第一和第二振荡信号之间的相位差; 解调器，被配置为执行所述接收信号的解调处理并生成包括在所述第一振荡信号中的第二相位的定时信息;第二相位比较器，被配置为检测所述第一和第二振荡信号之间的相位差;以及第一控制 电压发生器被配置为基于由第二相位比较器检测的相位差产生用于控制第二压控振荡器的相位和频率的第一控制电压。

公开(公告)号：US07718515B2

公开(公告)日：2010-05-18

申请号：US12073492

申请日：2008-03-06

Applicant: Kazuhide Abe

Inventor： Kazuhide Abe

IPC: H01L21/20

CPC classification number: H01L29/66712 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/3225 ,  H01L29/1608 ,  H01L29/66068

Abstract: The principal objects of the present invention are to provide structure of a semiconductor device capable of reducing a bowing of a wafer, and a method for fabricating the semiconductor device. The present invention is applied to a semiconductor device, which is fabricated with a semiconductor substrate having a silicon carbide (SiC) film. The method includes the steps of: forming the SiC film on a semiconductor wafer; discriminating a deformation condition of the semiconductor wafer; and forming grooves in the SiC film, the grooves having a shape determined in accordance with the deformation condition of the semiconductor wafer.

Abstract translation: 本发明的主要目的是提供能够减少晶片弯曲的半导体器件的结构以及制造半导体器件的方法。 本发明应用于半导体器件，其由具有碳化硅（SiC）膜的半导体衬底制造。 该方法包括以下步骤：在半导体晶片上形成SiC膜; 鉴别半导体晶片的变形状态; 以及在所述SiC膜中形成槽，所述槽具有根据所述半导体晶片的变形条件确定的形状。

公开(公告)号：US20090243725A1

公开(公告)日：2009-10-01

申请号：US12409926

申请日：2009-03-24

Applicant: Kazuhide ABE ,  Tadahiro Sasaki ,  Kazuhiko Itaya

Inventor： Kazuhide ABE ,  Tadahiro Sasaki ,  Kazuhiko Itaya

IPC: H03F3/185 ,  H01L25/065

CPC classification number: H03F3/195 ,  H01L23/585 ,  H01L23/66 ,  H01L29/0657 ,  H01L29/41758 ,  H01L29/4238 ,  H01L2223/6644 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first transistor unit including first field effect transistors with first gate electrodes electrically connected together, first sources electrically connected together, and first drains electrically connected together, the first gate electrodes being electrically connected to the first drains, a second transistor unit including second field effect transistors with second gate electrodes electrically connected together, second sources electrically connected together, and second drains electrically connected together, the second gate electrodes being electrically connected to the first gate electrodes, and dummy gate electrodes electrically isolated from the first gate electrodes and the second gate electrodes. The first gate electrodes, the second gate electrodes, and the dummy gate electrodes are arranged parallel to one another, and at least one dummy gate electrode is located between any one of the first gate electrodes and any one of the second gate electrodes.

Abstract translation: 半导体器件包括第一晶体管单元，其包括第一场效应晶体管，第一栅电极电连接在一起，电连接在一起的第一源和电连接在一起的第一漏极，第一栅电极电连接到第一漏极，第二晶体管单元 包括第二场效应晶体管，其中第二栅电极电连接在一起，第二源电连接在一起，第二漏极电连接在一起，第二栅电极电连接到第一栅电极，以及虚栅极与第一栅电极电隔离 和第二栅电极。 第一栅电极，第二栅电极和伪栅极彼此平行布置，并且至少一个虚拟栅电极位于第一栅极电极和第二栅极电极中的任一个之间。

公开(公告)号：US20080238550A1

公开(公告)日：2008-10-02

申请号：US11857737

申请日：2007-09-19

Applicant: Tadahiro SASAKI ,  Kazuhide Abe ,  Kazuhiko Itaya ,  Hideyuki Funaki

Inventor： Tadahiro SASAKI ,  Kazuhide Abe ,  Kazuhiko Itaya ,  Hideyuki Funaki

IPC: H03F3/16 ,  H03F3/68

CPC classification number: H03F3/604 ,  H01L21/823425 ,  H01L27/088 ,  H03F1/3205 ,  H03F3/16 ,  H03F3/607 ,  H03F3/72 ,  H03F2200/108 ,  H03F2200/451 ,  H03F2200/468 ,  H03F2200/543 ,  H03F2200/78 ,  H03F2203/7236

Abstract: A power amplifier includes: a first multi-finger FET formed on a semiconductor substrate; a second multi-finger FET formed on the semiconductor substrate; a first temperature detector which detects a channel temperature of the first FET; a second temperature detector which detects a channel temperature of the second FET; a third temperature detector which detects a temperature of the semiconductor substrate; a first detection circuit detecting a difference between an output of the first temperature detector and an output of the third temperature detector and converting the difference to thermoelectromotive force; a second detection circuit detecting a difference between an output of the second temperature detector and the output of the third temperature detector and converting the difference to thermoelectromotive force; and a comparator comparing outputs of the first and second detection circuits with each other to turn on one of the first and second switches and turn off the other.

Abstract translation: 功率放大器包括：形成在半导体衬底上的第一多指FET; 形成在半导体衬底上的第二多指FET; 第一温度检测器，其检测第一FET的通道温度; 第二温度检测器，其检测第二FET的通道温度; 第三温度检测器，其检测半导体衬底的温度; 第一检测电路，检测第一温度检测器的输出和第三温度检测器的输出之间的差异，并将差值转换为热电动势; 第二检测电路，检测第二温度检测器的输出与第三温度检测器的输出之间的差异，并将差值转换为热电动势; 以及比较器，将第一和第二检测电路的输出彼此进行比较，以打开第一和第二开关中的一个并且关闭另一个。

公开(公告)号：US20080233716A1

公开(公告)日：2008-09-25

申请号：US12073492

申请日：2008-03-06

Applicant: Kazuhide Abe

Inventor： Kazuhide Abe

IPC: H01L21/322

CPC classification number: H01L29/66712 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/3225 ,  H01L29/1608 ,  H01L29/66068

Abstract: The principal objects of the present invention are to provide structure of a semiconductor device capable of reducing a bowing of a wafer, and a method for fabricating the semiconductor device. The present invention is applied to a semiconductor device, which is fabricated with a semiconductor substrate having a silicon carbide (SiC) film. The method includes the steps of: forming the SiC film on a semiconductor wafer; discriminating a deformation condition of the semiconductor wafer; and forming grooves in the SiC film, the grooves having a shape determined in accordance with the deformation condition of the semiconductor wafer.

Abstract translation: 本发明的主要目的是提供能够减少晶片弯曲的半导体器件的结构以及制造半导体器件的方法。 本发明应用于半导体器件，其由具有碳化硅（SiC）膜的半导体衬底制造。 该方法包括以下步骤：在半导体晶片上形成SiC膜; 鉴别半导体晶片的变形状态; 以及在所述SiC膜中形成槽，所述槽具有根据所述半导体晶片的变形条件确定的形状。

公开(公告)号：US07215066B2

公开(公告)日：2007-05-08

申请号：US11196596

申请日：2005-08-04

Applicant: Takashi Kawakubo ,  Toshihiko Nagano ,  Kazuhide Abe ,  Michihiko Nishigaki

Inventor： Takashi Kawakubo ,  Toshihiko Nagano ,  Kazuhide Abe ,  Michihiko Nishigaki

IPC: H01L41/053

CPC classification number: H01H57/00 ,  H01G5/18 ,  H01G5/38 ,  H01H2057/006 ,  H01L41/094 ,  H01L41/0946 ,  H01L41/0953 ,  Y10S977/837

Abstract: A piezoelectric actuator includes a first beam including a first bottom electrode, a first piezoelectric film on the first bottom electrode, and a first top electrode on the first piezoelectric film, a fixed end assigned at an end of the first beam and fixed on a substrate, a connecting end assigned at another end of the first beam and suspended over a free space; and a second beam including a second piezoelectric film connected to the first piezoelectric film at the connecting end, a second bottom electrode under the second piezoelectric film, and a second top electrode on the second piezoelectric film, a working end assigned at an end of the second beam opposite to another end to which the connecting end is assigned and suspended over the free space; wherein a distance between centers of the fixed end and the working end is shorter than a distance from the working end to the connecting end.

Abstract translation: 压电致动器包括第一梁，该第一梁包括第一底电极，第一底电极上的第一压电膜和第一压电膜上的第一顶电极，分配在第一梁的端部并固定在基板上的固定端 ，分配在第一梁的另一端并悬挂在自由空间上的连接端; 以及第二光束，包括在连接端连接到第一压电膜的第二压电膜，第二压电膜下的第二底电极和第二压电膜上的第二顶电极，分配在第二压电膜的端部的工作端 第二梁相对于连接端被分配并悬挂在自由空间上的另一端; 其中固定端和工作端的中心之间的距离短于从工作端到连接端的距离。

公开(公告)号：US20060220083A1

公开(公告)日：2006-10-05

申请号：US11306387

申请日：2005-12-27

Applicant: Kazuhide Abe

Inventor： Kazuhide Abe

IPC: H01L29/94

CPC classification number: H01L27/11502 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76864 ,  H01L21/7687 ,  H01L21/76877 ,  H01L27/11507 ,  H01L28/65 ,  H01L28/75

Abstract: A semiconductor device includes a semiconductor substrate, a first electrode that is formed over said semiconductor substrate, a capacitive insulating film that is formed on the first electrode and is made of a metal oxide ferroelectric, a second electrode that is formed on the capacitive insulating film, an insulating film that has a first opening exposing a portion of an upper side of the second electrode and is formed so that it covers the first electrode, the capacitive insulating film, and the second electrode, a first barrier film having an amorphous structure which is formed inside the first opening and on the insulating film, and a wiring film that is formed over the first barrier film.

Abstract translation: 半导体器件包括半导体衬底，形成在所述半导体衬底上的第一电极，形成在第一电极上并由金属氧化物铁电体制成的电容绝缘膜，形成在电容绝缘膜上的第二电极 绝缘膜，其具有暴露第二电极的上侧的一部分并且形成为使得其覆盖第一电极，电容绝缘膜和第二电极的第一开口，具有非晶结构的第一阻挡膜， 形成在第一开口内部和绝缘膜上，以及形成在第一阻挡膜上的布线膜。

公开(公告)号：US20060055287A1

公开(公告)日：2006-03-16

申请号：US11196596

申请日：2005-08-04

Applicant: Takashi Kawakubo ,  Toshihiko Nagano ,  Kazuhide Abe ,  Michihiko Nishigaki

Inventor： Takashi Kawakubo ,  Toshihiko Nagano ,  Kazuhide Abe ,  Michihiko Nishigaki

IPC: H01L41/04

CPC classification number: H01H57/00 ,  H01G5/18 ,  H01G5/38 ,  H01H2057/006 ,  H01L41/094 ,  H01L41/0946 ,  H01L41/0953 ,  Y10S977/837

Abstract: A piezoelectric actuator includes a first beam including a first bottom electrode, a first piezoelectric film on the first bottom electrode, and a first top electrode on the first piezoelectric film, a fixed end assigned at an end of the first beam and fixed on a substrate, a connecting end assigned at another end of the first beam and suspended over a free space; and a second beam including a second piezoelectric film connected to the first piezoelectric film at the connecting end, a second bottom electrode under the second piezoelectric film, and a second top electrode on the second piezoelectric film, a working end assigned at an end of the second beam opposite to another end to which the connecting end is assigned and suspended over the free space; wherein a distance between centers of the fixed end and the working end is shorter than a distance from the working end to the connecting end.

Abstract translation: 压电致动器包括第一梁，该第一梁包括第一底电极，第一底电极上的第一压电膜和第一压电膜上的第一顶电极，分配在第一梁的端部并固定在基板上的固定端 ，分配在第一梁的另一端并悬挂在自由空间上的连接端; 以及第二光束，包括在连接端连接到第一压电膜的第二压电膜，第二压电膜下的第二底电极和第二压电膜上的第二顶电极，分配在第二压电膜的端部的工作端 第二梁相对于连接端被分配并悬挂在自由空间上的另一端; 其中固定端和工作端的中心之间的距离短于从工作端到连接端的距离。

公开(公告)号：US06924176B2

公开(公告)日：2005-08-02

申请号：US10103696

申请日：2002-03-25

Applicant: Toru Yoshie ,  Kazuhide Abe ,  Yusuke Harada

Inventor： Toru Yoshie ,  Kazuhide Abe ,  Yusuke Harada

IPC: H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/525 ,  H01L21/82 ,  H01L21/26 ,  H01L21/326

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A conductive layer which is formed on an insulative layer on a semiconductor substrate is connected to the semiconductor substrate via a through portion which passes through the insulative layer and reaches the semiconductor substrate. In a state where the conductive layer is electrically connected to the semiconductor substrate via the through portion, a patterning process using a plasma etching is performed on the conductive layer, thereby forming a conductive path. After the formation of the conductive path, a heating process is performed on the substrate or the conductive path in order to disconnect the electrical connection between the through portion and the substrate by a reaction between the through portion and the semiconductor substrate which is in contact therewith.

Abstract translation: 形成在半导体衬底上的绝缘层上的导电层通过穿过绝缘层并到达半导体衬底的贯穿部连接到半导体衬底。 在导电层通过贯通部分电连接到半导体衬底的状态下，在导电层上进行使用等离子体蚀刻的图案化工艺，从而形成导电路径。 在形成导电路径之后，在衬底或导电路径上进行加热处理，以便通过与其接触的通孔部分和半导体衬底之间的反应而断开通孔部分和衬底之间的电连接 。