公开(公告)号：US20130127007A1

公开(公告)日：2013-05-23

申请号：US13303946

申请日：2011-11-23

申请人： Che-Hao Chuang ,  Kun-Hsien Lin ,  Ryan Hsin-Chin Jiang

发明人： Che-Hao Chuang ,  Kun-Hsien Lin ,  Ryan Hsin-Chin Jiang

IPC分类号： H01L29/06

CPC分类号： H01L27/0296 ,  H01L29/8613 ,  H01L29/866

摘要： A transient voltage suppressor without leakage current is disclosed, which comprises a P-substrate. There is an N-type epitaxial layer formed on the P-substrate, and a first N-heavily doped area, a first P-heavily doped area, an electrostatic discharge (ESD) device and at least one deep isolation trench are formed in the N-epitaxial layer. A first N-buried area is formed in the bottom of the N-epitaxial layer to neighbor the P-substrate and located below the first N-heavily doped area and the first P-heavily doped area. The ESD device is coupled to the first N-heavily doped area. The deep isolation trench is not only adjacent to the first N-heavily doped area, but has a depth greater than a depth of the first N-buried area, thereby separating the first N-buried area and the ESD device.

摘要翻译： 公开了一种无泄漏电流的瞬态电压抑制器，其包括P型衬底。 在P基板上形成有N型外延层，在第一N重掺杂区，第一P重掺杂区，静电放电（ESD）器件和至少一个深隔离沟槽中形成第一N重掺杂区， N外延层。 在N外延层的底部形成第一N区，以邻近P衬底并且位于第一N重掺杂区和第一P重掺杂区的下方。 ESD器件耦合到第一N重掺杂区域。 深隔离沟槽不仅与第一N重掺杂区相邻，而且具有大于第一N埋入区深度的深度，从而分离第一N埋区和ESD器。

公开(公告)号：US20120292721A1

公开(公告)日：2012-11-22

申请号：US13109599

申请日：2011-05-17

申请人： Hsin-Fu Huang ,  Kun-Hsien Lin ,  Chi-Mao Hsu ,  Min-Chuan Tsai ,  Tzung-Ying Lee ,  Chin-Fu Lin

发明人： Hsin-Fu Huang ,  Kun-Hsien Lin ,  Chi-Mao Hsu ,  Min-Chuan Tsai ,  Tzung-Ying Lee ,  Chin-Fu Lin

IPC分类号： H01L29/78 ,  H01L21/285

CPC分类号： H01L29/78 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： A method of fabricating a semiconductor device includes following steps. A substrate is provided, wherein a first dielectric layer having a trench therein is formed on the substrate, a source/drain region is formed in the substrate at two sides of the trench, and a second dielectric layer is formed on the substrate in the trench. A first physical vapor deposition process is performed to form a Ti-containing metal layer in the trench. A second physical vapor deposition process is performed to form an Al layer on the Ti-containing metal layer in the trench. A thermal process is performed to anneal the Ti-containing metal layer and the Al layer so as to form a work function metal layer. A metal layer is formed to fill the trench.

摘要翻译： 制造半导体器件的方法包括以下步骤。 提供了一种衬底，其中在衬底上形成有沟槽的第一电介质层，在沟槽的两侧在衬底中形成源极/漏极区，并且在沟槽中的衬底上形成第二电介质层 。 进行第一物理气相沉积工艺以在沟槽中形成含Ti金属层。 进行第二物理气相沉积工艺以在沟槽中的含Ti金属层上形成Al层。 进行热处理以使含Ti金属层和Al层退火以形成功函数金属层。 形成金属层以填充沟槽。

公开(公告)号：US20120241903A1

公开(公告)日：2012-09-27

申请号：US13072138

申请日：2011-03-25

申请人： Yu-Shu SHEN ,  Kun-Hsien Lin ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang

发明人： Yu-Shu SHEN ,  Kun-Hsien Lin ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang

IPC分类号： H01L29/66

CPC分类号： H01L27/0255 ,  H01L29/861

摘要： A low capacitance transient voltage suppressor is disclosed. The suppressor comprises an N-type heavily doped substrate and an epitaxial layer formed on the substrate. At least one steering diode structure formed in the epitaxial layer comprises a diode lightly doped well and a first P-type lightly doped well, wherein a P-type heavily doped area is formed in the diode lightly doped well and a first N-type heavily doped area and a second P-type heavily doped area are formed in the first P-type lightly doped well. A second P-type lightly doped well having two N-type heavily doped areas is formed in the epitaxial layer. In addition, an N-type heavily doped well and at least one deep isolation trench are formed in the epitaxial layer, wherein the trench has a depth greater than or equal to depths of all the doped wells, so as to separate at least one doped well.

摘要翻译： 公开了一种低电容瞬态电压抑制器。 抑制器包括N型重掺杂衬底和形成在衬底上的外延层。 形成在外延层中的至少一个转向二极管结构包括二极管轻掺杂阱和第一P型轻掺杂阱，其中在二极管轻掺杂阱中形成P型重掺杂区，并且第一N型重掺杂阱 在第一P型轻掺杂阱中形成掺杂区域和第二P型重掺杂区域。 在外延层中形成具有两个N型重掺杂区的第二P型轻掺杂阱。 此外，在外延层中形成N型重掺杂阱和至少一个深隔离沟槽，其中沟槽的深度大于或等于所有掺杂阱的深度，以便分离至少一个掺杂的 好。

公开(公告)号：US20120018778A1

公开(公告)日：2012-01-26

申请号：US12840749

申请日：2010-07-21

申请人： ZI-PING CHEN ,  Kun-Hsien Lin ,  Ryan Hsin-Chin Jiang

发明人： ZI-PING CHEN ,  Kun-Hsien Lin ,  Ryan Hsin-Chin Jiang

IPC分类号： H01L27/06

CPC分类号： H01L27/0259

摘要： A new ESD protection device with an integrated-circuit vertical transistor structure is disclosed, which includes a heavily doped p-type substrate (P+ substrate), a n-type well (N well) in the P+ substrate, a heavily doped p-type diffusion (P+ diffusion) in the N well, a heavily doped n-type diffusion (N+ diffusion) in the N well, and a p-type well (P well) surrounding the N well in the P+ substrate. A bond pad is connected to both the P+ and N+ diffusions, and a ground is coupled to the P+ substrate. Another P+ diffusion is implanted in the N well or another N+ diffusion is implanted in the P well to form a Zener diode, which behaves as a trigger for the PNP transistor when a positive ESD zaps. A parasitic diode is formed at the junction between the P+ substrate and the N well, to bypass a negative ESD stress on the bond pad.

摘要翻译： 公开了一种具有集成电路垂直晶体管结构的新型ESD保护器件，其包括重掺杂p型衬底（P +衬底），P +衬底中的n型阱（N阱），重掺杂p型衬底 N阱中的扩散（P +扩散），N阱中的重掺杂n型扩散（N +扩散）以及P +衬底中N阱周围的p型阱（P阱）。 接合焊盘连接到P +和N +扩散两者，并且接地耦合到P +衬底。 将另一个P +扩散注入到N阱中，或者将另一个N +扩散注入到P阱中以形成齐纳二极管，当正ESD成像时，其作为PNP晶体管的触发器。 在P +衬底和N阱之间的接合处形成寄生二极管，以绕过接合焊盘上的负ESD应力。

公开(公告)号：US20120014027A1

公开(公告)日：2012-01-19

申请号：US12836745

申请日：2010-07-15

申请人： Kun-Hsien LIN ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang

发明人： Kun-Hsien LIN ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang

IPC分类号： H02H3/22

CPC分类号： H02H9/046 ,  H05K1/0259

摘要： A transient voltage suppressor (TVS) for multiple pin assignments is disclosed. The suppressor comprises at least two cascade-diode circuits in parallel to each other and an electrostatic-discharge clamp element in parallel to each cascade-diode circuit and connected with a low voltage. One cascade-diode circuit is connected with a high voltage, and the other cascade-diode circuits are respectively connected with I/O pins. Each cascade-diode circuit further comprises a first diode and a second diode cascaded to the first diode, wherein a node between the first diode and the second diode is connected with the high voltage or the one I/O pin. The design of the present invention can meet several bounding requirements. It is flexible different pin assignments of TVS parts.

摘要翻译： 公开了一种用于多个引脚分配的瞬态电压抑制器（TVS）。 抑制器包括彼此并联的至少两个级联二极管电路和与每个级联二极管电路并联并与低电压连接的静电放电钳位元件。 一个级联二极管电路与高电压连接，其他级联二极管电路分别与I / O引脚相连。 每个级联二极管电路还包括级联到第一二极管的第一二极管和第二二极管，其中第一二极管和第二二极管之间的节点与高电压或一个I / O引脚连接。 本发明的设计可以满足多个限制要求。 它是TVS零件的灵活不同的引脚分配。

公开(公告)号：US07098511B2

公开(公告)日：2006-08-29

申请号：US10973264

申请日：2004-10-27

申请人： Ming-Dou Ker ,  Kun-Hsien Lin

发明人： Ming-Dou Ker ,  Kun-Hsien Lin

IPC分类号： H01L23/62

CPC分类号： H01L27/0292 ,  H01L27/0251

摘要： The claimed invention discloses an ESD protection circuit that is applied to an IC with power-down-mode operation. When the IC goes into power-down-mode operation, leakage current and charging from the I/O pad to the VDD power line could be prevented by applying the present invention. Therefore, the malfunction of the IC can be avoided. There still have two ESD clamp circuits respectively connected between the VDD power line and the VSS power line and between ESD bus line and VSS power line, so as to achieve the whole chip ESD protection scheme. The present invention can prevent ESD protection circuit from resulting in leakage current or malfunction under power-down-mode operation, and moreover achieve whole chip ESD protection scheme.

摘要翻译： 所要求保护的发明公开了一种ESD保护电路，其被应用于具有掉电模式操作的IC。 当IC进入掉电模式操作时，可以通过应用本发明来防止漏电流和从I / O焊盘到VDD电源线的充电。 因此，可以避免IC的故障。 在VDD电源线和VSS电源线之间以及ESD总线与VSS电源线之间分别连接有两个ESD钳位电路，从而实现了整个芯片的ESD保护方案。 本发明可以防止ESD保护电路在掉电模式下产生漏电流或故障，而且可实现全芯片ESD保护方案。

公开(公告)号：US20050174707A1

公开(公告)日：2005-08-11

申请号：US10973264

申请日：2004-10-27

申请人： Ming-Dou Ker ,  Kun-Hsien Lin

发明人： Ming-Dou Ker ,  Kun-Hsien Lin

IPC分类号： H01L23/60 ,  H01L23/62 ,  H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0292 ,  H01L27/0251

摘要： The claimed invention discloses an ESD protection circuit that is applied to an IC with power-down-mode operation. When the IC goes into power-down-mode operation, leakage current and charging from the I/O pad to the VDD power line could be prevented by applying the present invention. Therefore, the malfunction of the IC can be avoided. There still have two ESD clamp circuits respectively connected between the VDD power line and the VSS power line and between ESD bus line and VSS power line, so as to achieve the whole chip ESD protection scheme. The present invention can prevent ESD protection circuit from resulting in leakage current or malfunction under power-down-mode operation, and moreover achieve whole chip ESD protection scheme.

摘要翻译： 所要求保护的发明公开了一种ESD保护电路，其被应用于具有掉电模式操作的IC。 当IC进入掉电模式操作时，可以通过应用本发明来防止漏电流和从I / O焊盘到VDD电源线的充电。 因此，可以避免IC的故障。 在VDD电源线和VSS电源线之间以及ESD总线与VSS电源线之间分别连接有两个ESD钳位电路，从而实现了整个芯片的ESD保护方案。 本发明可以防止ESD保护电路在掉电模式下产生漏电流或故障，而且可实现全芯片ESD保护方案。

公开(公告)号：US20050122645A1

公开(公告)日：2005-06-09

申请号：US10726641

申请日：2003-12-04

申请人： Ming-Dou Ker ,  Kun-Hsien Lin

发明人： Ming-Dou Ker ,  Kun-Hsien Lin

IPC分类号： H05K1/02 ,  H05K1/11 ,  H05K9/00 ,  H02H9/00

CPC分类号： H05K1/0259 ,  H05K1/117 ,  H05K9/0067 ,  H05K2201/09354 ,  H05K2201/094 ,  H05K2201/10689

摘要： An interface device coupled to a board on which integrated circuits are mounted for providing electrostatic discharge protection for the integrated circuits that comprises a plurality of first contact members, each of the first contact members including one end connected to the board and the other end to connect to an external device, and at least one second contact member connected to a voltage line of a voltage level, wherein the at least one second contact member includes a length greater than that of each of the first contact members.

摘要翻译： 一种接口装置，其耦合到其上安装有集成电路的板，用于为包括多个第一接触构件的集成电路提供静电放电保护，所述第一接触构件中的每一个包括连接到所述板的一端和用于连接的另一端 连接到电压电平的电压线的至少一个第二接触构件，其中所述至少一个第二接触构件的长度大于每个所述第一接触构件的长度。

公开(公告)号：US06867461B1

公开(公告)日：2005-03-15

申请号：US10814128

申请日：2004-04-01

申请人： Ming-Dou Ker ,  Kun-Hsien Lin

发明人： Ming-Dou Ker ,  Kun-Hsien Lin

IPC分类号： H01L23/60 ,  H01L23/62 ,  H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0292 ,  H01L27/0251

摘要： The claimed invention discloses an ESD protection circuit that is applied to an IC with power-down-mode operation. When the IC goes into power-down-mode operation, leakage current and charging from the I/O pad to the VDD power line could be prevented by applying the present invention. Therefore, the malfunction of the IC can be avoided. There still have two ESD clamp circuits respectively connected between the VDD power line and the VSS power line and between ESD bus line and VSS power line, so as to achieve the whole chip ESD protection scheme. The present invention can prevent ESD protection circuit from resulting in leakage current or malfunction under power-down-mode operation, and moreover achieve whole chip ESD protection scheme.

公开(公告)号：US20150000236A1

公开(公告)日：2015-01-01

申请号：US13502747

申请日：2012-03-22

申请人： Weibing Yang ,  Chun-hao Wu ,  Kun-hsien Lin ,  Yongqiang Wang ,  Erqing Zhu ,  Xiande Li ,  Minghu Qi ,  Zenghong Chen ,  Zhenhua Guo ,  Yunshao Jiang

发明人： Weibing Yang ,  Chun-hao Wu ,  Kun-hsien Lin ,  Yongqiang Wang ,  Erqing Zhu ,  Xiande Li ,  Minghu Qi ,  Zenghong Chen ,  Zhenhua Guo ,  Yunshao Jiang

IPC分类号： F24F13/28 ,  B01D46/00

CPC分类号： F24F13/28 ,  B01D29/52 ,  B01D46/0019 ,  B01D46/10 ,  B01D2279/51 ,  E04B9/064 ,  E04B9/244 ,  F24F3/1603 ,  F24F3/1607 ,  F24F3/161 ,  F24F2221/14

摘要： The present invention discloses a suspended ceiling filtration apparatus, which includes filtration units. The filtration unit includes a filtration part, two horizontal strip support legs and two longitudinal strip support legs. A support plate protrudes from the support legs. The filtration part is placed on the support plate, and a buffer filling part is disposed between the filtration part and the support plate. The buffer filling part is utilized to self-adaptively swell and shrink relative to the support plate according to a weight of the supported filtration part, the buffer filling part fills a gap between the support plate and the filtration part.

摘要翻译： 本发明公开了一种悬吊天花板过滤装置，其包括过滤单元。 过滤单元包括过滤部分，两个水平条带支撑腿和两个纵向条支撑腿。 支撑板从支撑腿突出。 将过滤部件放置在支撑板上，并且缓冲填充部分设置在过滤部分和支撑板之间。 缓冲填充部分根据支撑的过滤部分的重量被用于相对于支撑板自适应地膨胀和收缩，缓冲填充部分填充支撑板和过滤部分之间的间隙。