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    SYSTEM COMPRISING A GATE DRIVER
    31.
    发明申请
    SYSTEM COMPRISING A GATE DRIVER 有权

    公开(公告)号：US20240380307A1

    公开(公告)日：2024-11-14

    申请号：US18652889

    申请日：2024-05-02

    Applicant: NXP USA, INC.

    Inventor： Jerry Rudiak ,  Burton Jesse Carpenter ,  Fred T. Brauchler

    IPC: H02M1/088 ,  H02M7/00 ,  H02M7/537

    Abstract: A system comprising a first gate driver comprising: a first die including a first controller for controlling a gate of a first power switch; a second die arranged with the first die and galvanically isolated from the first die, the second die comprising communication circuitry; wherein the first die includes a first connection element and the second die includes a second connection element, wherein the first and second connection elements are configured to provide a communication channel between the galvanically isolated first die and second die; and wherein the second die comprises at least one communication terminal for coupling to a second gate driver comprising a second controller, the second controller for controlling a gate of a second power switch; wherein the communication channel provides for communication between the first controller and the second controller.

    MEMORY CONTROLLER WHICH IMPLEMENTS PARTIAL WRITES WITH ERROR SIGNALING
    32.
    发明申请
    MEMORY CONTROLLER WHICH IMPLEMENTS PARTIAL WRITES WITH ERROR SIGNALING 有权

    公开(公告)号：US20240370334A1

    公开(公告)日：2024-11-07

    申请号：US18480992

    申请日：2023-10-04

    Applicant: NXP USA, Inc.

    Inventor： Martin Mienkina ,  Quyen Pho ,  Avni Arora

    IPC: G06F11/10 ,  G06F11/07 ,  G06F13/16

    Abstract: A requestor of a data processing system provides read access requests, full write access requests with corresponding full write data each having a full-width data size, and partial write access requests with corresponding partial write data each having a partial-width data size onto a system interconnect. A memory array stores write data and corresponding error correction code (ECC) check bits in response to write access requests and provides read data and corresponding ECC check bits for the read data in response to read access requests. A memory controller executes a read-modify-write (RMW) sequence between a store buffer and the memory array to implement a partial write transaction in response to a partial write access request, in which the memory controller stores the partial write data into the store buffer upon receiving the partial write access request and suppresses signaling of ECC errors to the requestor during the RMW sequence.

    DYNAMIC CHANNEL SWITCH OPERATION
    33.
    发明公开
    DYNAMIC CHANNEL SWITCH OPERATION 审中-公开

    公开(公告)号：US20240365383A1

    公开(公告)日：2024-10-31

    申请号：US18644734

    申请日：2024-04-24

    Applicant: NXP USA, INC.

    Inventor： Liwen CHU ,  Rui CAO ,  Kiseon RYU ,  Huizhao WANG ,  Hongyuan ZHANG

    IPC: H04W74/0816 ,  H04L1/00 ,  H04W74/08

    CPC classification number: H04W74/0816 ,  H04L1/0068 ,  H04W74/0866

    Abstract: A method of method of dynamic channel switching by a station (STA), including: receiving a resource unit (RU) allocation in an initial frame exchange; determining that the STA cannot operate in its operating BW covering a primary channel based upon the RU allocation; switching to secondary channel(s) per an RU allocated to it to carry out communication by the STA during a transmit opportunity (TXOP); carrying out the communication during the TXOP; and switching back to the primary channel no later than an end of the TXOP if detecting that an AP will not do the initial frame exchange with it in the secondary channel(s) within the TXOP.

    Switch with cascode arrangement
    35.
    发明授权
    Switch with cascode arrangement 有权

    公开(公告)号：US12132473B2

    公开(公告)日：2024-10-29

    申请号：US18183006

    申请日：2023-03-13

    Applicant: NXP USA, Inc.

    Inventor： David Edward Bien ,  Xu Jason Ma

    IPC: H03K17/082

    CPC classification number: H03K17/0822

    Abstract: A switching device may include an input terminal, an output terminal, a primary switching transistor electrically coupled between the input terminal and the output terminal, and a cascode arrangement electrically coupled between the primary switching transistor and the input terminal. The cascode arrangement may include multiple cascode transistors, each having gate terminals coupled to nodes of a voltage divider that is coupled between a positive voltage supply and a reference voltage supply. Emitter-follower bipolar junction transistors (BJTs) may be configured to control voltages at the gate terminals of the primary switching transistor and the cascode transistors to accommodate changes in the output voltage at the output terminal.

    Fault detection during entry to or exit from low power mode
    39.
    发明授权
    Fault detection during entry to or exit from low power mode 有权

    公开(公告)号：US12124309B2

    公开(公告)日：2024-10-22

    申请号：US18055915

    申请日：2022-11-16

    Applicant: NXP USA, Inc.

    Inventor： Kumar Abhishek ,  Subhashrahul Shekhar ,  Aditya Musunuri ,  Yi Zheng

    IPC: G06F1/00 ,  G06F1/30 ,  G06F1/3296 ,  G06F11/07 ,  G06F11/30

    CPC classification number: G06F1/30 ,  G06F1/3296 ,  G06F11/0772

    Abstract: A system-on-chip (SoC) having a switchable power domain capable of being placed in a standby mode during which a power supply of the switchable power domain is gated and having an always-on power domain. The always-on power domain includes an input sampling circuit, and the switchable power domain includes an input/output (IO) circuit configured to, during normal operation, receive data at a corresponding signal pin when an input buffer of the IO circuit is enabled, in which the corresponding signal pin is coupled to the input sampling circuit. The input sampling circuit is configured to, while the switchable power domain is entering the standby mode but before the power supply is gated, provide an override input enable signal to enable the input buffer of the IO circuit, sample an input bit value on the corresponding signal pin, and store the sampled bit value to provide an injection current fault indicator.

    INTEGRATED CIRCUIT WITH TIMING CORRECTION CIRCUITRY
    40.
    发明公开
    INTEGRATED CIRCUIT WITH TIMING CORRECTION CIRCUITRY 审中-公开

    公开(公告)号：US20240345163A1

    公开(公告)日：2024-10-17

    申请号：US18354925

    申请日：2023-07-19

    Applicant: NXP USA, Inc.

    Inventor： Shilpa Gupta ,  Rishi Bhooshan ,  Anis Mahmoud Jarrar ,  David Russell Tipple ,  Hadi Ahmadi Balef

    IPC: G01R31/3185 ,  G01R31/317 ,  G01R31/3193

    CPC classification number: G01R31/318525 ,  G01R31/31727 ,  G01R31/31932

    Abstract: A margin sensing circuit coupled to a flip flop of a critical data path includes a delay generator, a selector circuit which selects a delayed data output from the delay generator, a shadow latch corresponding to the flip flop, a comparator circuit which provides a match error indicator based on a comparison between a latched data output from the flip flop and a latched shadow output from the shadow latch, and an error latch to provide an error indicator based on the match error indicator. A correcting circuit includes a clock delay generator configured to receive a clock and provide a plurality of delayed clocks, and a clock selector circuit to select a delayed clock of the plurality of delayed clocks based on a set of clock select signals, in which each of the flip flop and the shadow latch are clocked by the selected delayed clock.

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