公开(公告)号：US11935809B2

公开(公告)日：2024-03-19

申请号：US18064607

申请日：2022-12-12

申请人： NXP USA, INC.

发明人： Zhiwei Gong ,  Scott M. Hayes ,  Michael B. Vincent ,  Betty Hill-Shan Yeung ,  Rushik P. Tank ,  Kabir Mirpuri

IPC分类号： H01L23/36 ,  H01L21/48 ,  H01L23/367 ,  H01L23/552 ,  H01L23/66

CPC分类号： H01L23/3672 ,  H01L21/4882 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6677

摘要： A cost-effective process and structure is provided for a thermal dissipation element for semiconductor device packages incorporating antennas that can incorporate RF/EMI shielding from the antenna elements. Certain embodiments provide incorporated antenna element structures as part of the same process. These features are provided using a selectively-plated thermal dissipation structure that is formed to provide shielding around semiconductor device dies that are part of the package. In some embodiments, the thermal dissipation structure is molded to the semiconductor device, thereby permitting a thermally efficient close coupling between a device die requiring thermal dissipation and the dissipation structure itself.

公开(公告)号：US11791283B2

公开(公告)日：2023-10-17

申请号：US17230098

申请日：2021-04-14

申请人： NXP USA, INC.

发明人： Scott M. Hayes ,  Michael B. Vincent ,  Zhiwei Gong ,  Richard Te Gan ,  Vivek Gupta

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L21/683

CPC分类号： H01L23/562 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835

摘要： A method of manufacturing a semiconductor device packaging panel is provided. The method includes forming a panel having an active side and a backside. The panel includes a plurality of semiconductor die encapsulated with an encapsulant. An active surface of the semiconductor die is exposed on the active side of the panel. A warpage control carrier is attached onto the backside of the panel. The warpage control carrier includes an electroactive element configured for substantially flattening the panel while a control voltage is applied to the electroactive element.

公开(公告)号：US11557525B2

公开(公告)日：2023-01-17

申请号：US17330336

申请日：2021-05-25

申请人： NXP USA, Inc.

发明人： Zhiwei Gong ,  Scott M. Hayes ,  Michael B. Vincent ,  Betty Hill-Shan Yeung ,  Rushik P. Tank ,  Kabir Mirpuri

IPC分类号： H01L23/36 ,  H01L21/48 ,  H01L23/367 ,  H01L23/552 ,  H01L23/66

摘要： A cost-effective process and structure is provided for a thermal dissipation element for semiconductor device packages incorporating antennas that can incorporate RF/EMI shielding from the antenna elements. Certain embodiments provide incorporated antenna element structures as part of the same process. These features are provided using a selectively-plated thermal dissipation structure that is formed to provide shielding around semiconductor device dies that are part of the package. In some embodiments, the thermal dissipation structure is molded to the semiconductor device, thereby permitting a thermally efficient close coupling between a device die requiring thermal dissipation and the dissipation structure itself.

公开(公告)号：US11031681B2

公开(公告)日：2021-06-08

申请号：US16446861

申请日：2019-06-20

申请人： NXP USA, INC.

发明人： Michael B. Vincent ,  Scott M. Hayes ,  Zhiwei Gong ,  Stephen Ryan Hooper ,  Pascal Oberndorff ,  Walter Parmon

IPC分类号： H01Q1/32 ,  H01L23/66 ,  H01L23/498 ,  H01Q1/22 ,  H01Q13/20 ,  H01L23/00

摘要： A method of manufacturing a packaged semiconductor device is provided. The method includes attaching a semiconductor die to a package substrate. A bond pad of the semiconductor die is coupled to an antenna radiator formed on the package substrate. A waveguide is attached to the package substrate. An opening of the waveguide includes sidewalls substantially surrounding the antenna radiator. An epoxy material is deposited over at least a portion of the package substrate while leaving the opening void of epoxy material.

公开(公告)号：US20210035927A1

公开(公告)日：2021-02-04

申请号：US16524596

申请日：2019-07-29

申请人： NXP USA, Inc.

发明人： Michael B. Vincent ,  Scott M. Hayes ,  Zhiwei Gong ,  Stephen Ryan Hooper

IPC分类号： H01L23/66 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01Q1/22

摘要： A semiconductor device package that incorporates a waveguide usable for high frequency applications, such as radar and millimeter wave is provided. Embodiments employ a rigid-flex printed circuit board structure that can be folded to form the waveguide while, at the same time, mounting one or more semiconductor device die or packages. Embodiments reduce both the area of the mounted package and the distance signals need to travel between the semiconductor device die and antennas associated with the waveguide.

公开(公告)号：US20180006001A1

公开(公告)日：2018-01-04

申请号：US15704616

申请日：2017-09-14

申请人： NXP USA, INC.

发明人： MICHAEL B. VINCENT ,  Zhiwei Gong ,  Scott M. Hayes

IPC分类号： H01L25/10 ,  H01L25/00

CPC分类号： H01L25/105 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/00014

摘要： A packaged semiconductor structure includes an interconnect layer and a first microelectronic device on a first major surface of the interconnect layer. The structure also includes a substrate having a cavity, wherein the cavity is defined by a vertical portion and a horizontal portion, wherein the vertical portion surrounds the first device, the horizontal portion is over the first device, and the first device is between the horizontal portion and the first major surface of the interconnect layer such that the first device is in the cavity. The structure further includes a second microelectronic device attached to the horizontal portion of the substrate, and encapsulant on the interconnect layer and surrounding the first device, the substrate, and the second device, such that the substrate is embedded in the encapsulant.

公开(公告)号：US11728285B2

公开(公告)日：2023-08-15

申请号：US17412327

申请日：2021-08-26

申请人： NXP USA, INC.

发明人： Vivek Gupta ,  Michael B. Vincent ,  Scott M. Hayes ,  Richard Te Gan ,  Zhiwei Gong

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L23/13 ,  H01L21/56

CPC分类号： H01L23/562 ,  H01L21/481 ,  H01L21/4807 ,  H01L21/4878 ,  H01L21/561 ,  H01L23/13

摘要： A method of manufacturing a carrier for semiconductor device packaging is provided. The method includes forming a carrier having a plurality of plateau regions separated by a plurality of channels. The carrier is configured and arranged to support a plurality of semiconductor die during a packaging operation. The plurality of channels is filled with a material configured to control warpage of the carrier.

公开(公告)号：US10163874B2

公开(公告)日：2018-12-25

申请号：US15704616

申请日：2017-09-14

申请人： NXP USA, INC.

发明人： Michael B. Vincent ,  Zhiwei Gong ,  Scott M. Hayes

IPC分类号： H01L25/00 ,  H01L25/10 ,  H01L23/00 ,  H01L21/56 ,  H01L25/16

摘要： A packaged semiconductor structure includes an interconnect layer and a first microelectronic device on a first major surface of the interconnect layer. The structure also includes a substrate having a cavity, wherein the cavity is defined by a vertical portion and a horizontal portion, wherein the vertical portion surrounds the first device, the horizontal portion is over the first device, and the first device is between the horizontal portion and the first major surface of the interconnect layer such that the first device is in the cavity. The structure further includes a second microelectronic device attached to the horizontal portion of the substrate, and encapsulant on the interconnect layer and surrounding the first device, the substrate, and the second device, such that the substrate is embedded in the encapsulant.

公开(公告)号：US10068841B2

公开(公告)日：2018-09-04

申请号：US15630633

申请日：2017-06-22

申请人： NXP USA, Inc.

发明人： Zhiwei Gong ,  Wei Gao

IPC分类号： H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/16 ,  H05K1/11 ,  H05K3/34 ,  H05K1/18

摘要： A semiconductor device assembly includes an interposer having an opening extending from a first major surface to a second major surface of the interposer and a plurality of external connectors on the second major surface. The first major surface of the interposer is attached to a packaged semiconductor device. The opening of the interposer exposes the packaged semiconductor device.

公开(公告)号：US20180177049A1

公开(公告)日：2018-06-21

申请号：US15380054

申请日：2016-12-15

申请人： NXP USA, INC.

发明人： Michael B. Vincent ,  Zhiwei Gong ,  Scott M. Hayes

IPC分类号： H05K1/11 ,  H05K3/42 ,  H05K3/00 ,  H05K3/28 ,  H05K3/34 ,  H05K1/18 ,  H01L21/48 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

CPC分类号： H05K1/115 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/49838 ,  H05K1/145 ,  H05K1/181 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/284 ,  H05K3/341 ,  H05K3/3436 ,  H05K3/42 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/09645 ,  H05K2201/10378 ,  H05K2201/10977 ,  H05K2203/1178 ,  H05K2203/1316 ,  H05K2203/1327 ,  Y10T29/49165

摘要： A plated hole with a sidewall plating. The plated hole has a vent opening that has a sidewall of non-conductive material that is not plated. During attachment of a joint conductive material such as solder to the sidewall plating, gasses generated from the attachment process are outgassed through the vent opening.